ABRIDGED DATA SHEET

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108

7 of 16

4 Block Diagram

Figure 4-1. Top-Level Block Diagram

SD_D[31:0]

SD_DQM[3:0]

SD_A[11:0]

SD_BA[1:0]

SD_CLK

SD_CS_N

SD_WE_N

SD_RAS_N

SD_CAS_N

CLK_HIGH

H_D[31:1]

H_AD[24:1]

H_CS_N

H_R_W_N

H_WR_BE[0]_N / SPI_CLK

H_READY_N

H_INT[1:0]

DATA_31_16_N

RST_SYS_N

JTMS

JTCLK

JTDI

JTDO

JTRST_N

MCLK

RESREF

TCLKOn

CLK_CMN

SCEN

STMD

MBIST_EN

MBIST_DONE

MBIST_FAIL

HIZ_EN

E1CLK

T1CLK

B8ZS/HDB3

Decoder

E1CLK

T1CLK

RCLKn (out)/RCLKFn (in)

RDATFn

Rx Elastic Store

TDATFn

B8ZS/HDB3

Encoder

Tx Elastic Store

TCLKFn

Jitter Attenuator

RSYNCn

RLOFn/RLOSn

RSERn

RFSYNCn/RMSYNCn

TDMn_RCLK

TDMn_RX

TDMn_RSIG_RTS

TSYSCLKn/ECLKn

TSERn

TSYNCn/TSSYNCn

TDMn_TX

TDMn_ACLK

TDMn_TSIG_CTS

TDMn_TX_MF_CD

TDMn_TX_SYNC

TDMn_TCLK

clk

clk

neg

neg

pos/dat

0

1

0

1

LIUDn

LIUDn

LIUDn

clk

neg

pos/dat

pos/dat

clk

neg

pos/dat

88

8

1 of 8 ports

all 8 ports

88

8

TDM Cross-Connection

and External Interfaces

TDMn_RX_SYNC

88

8

8

8

8

8

8

Control

Bank Select

Address

Byte Enable Mask

Data

8

8

RSYSCLKn

8

8

8

8

RCLK

8

8

8

H_CPU_SPI_N

H_D[0] / SPI_MISO

H_WR_BE[1]_N / SPI_MOSI

H_WR_BE[2]_N / SPI_SEL_N

H_WR_BE[3]_N / SPI_CI