DS2782

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Note 1:

Note 2:

Note 3:

Factory calibrated accuracy. Higher accuracy can be achieved by in-system calibration by the user.

Note 4:

Accumulation bias register set to 00h.

Note 5:

Parameters guaranteed by design.

Note 6:

Timing must be fast enough to prevent the DS2782 from entering sleep mode due to bus low for period >

Note 7:

Note 8:

signal.

Note 9:

This device internally provides a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of

the SCL signal) to bridge the undefined region of the falling edge of SCL.

Note 10:

Filters on SDA and SCL suppress noise spikes at the input buffers and delay the sampling instant.

Note 11:

Figure 1. I