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DS3106LN Datasheet(PDF) 7 Page - Maxim Integrated Products |
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DS3106LN Datasheet(HTML) 7 Page - Maxim Integrated Products |
7 / 87 page ____________________________________________________________________________________________ DS3106 19-4629; Rev 3; 5/09 7 of 87 2. Application Example Figure 2-1. Typical Application Example To SONET/SDH framers, Clock Multiplying APLLs, etc. on the Line Card T0 DPLL Input Clock Selector, Divider, Monitor From Master Timing Card IC3 IC4 OC3 19.44 MHz OC6 prog. bandwidth, manual reference switching, holdover, etc. DS3106 Output Clock Synthesizer and Selector 19.44 MHz 155.52MHz differential 19.44 MHz XO or TCXO From Slave Timing Card 3. Block Diagram Figure 3-1. Block Diagram T0 DPLL (Filtering, Holdover, Frequency Conversion) Master Clock Generator OC6 POS/NEG FSYNC MFSYNC IC3 IC4 Microprocessor Port (SPI Serial) and HW Control and Status Pins Local Oscillator REFCLK JTAG Input Clock Selector, Divider and Monitor Output Clock Synthesizer and Selector (Muxes, 7 DFS Blocks, 3 APLLs, Output Dividers) OC3 JTRST* JTMS JTCLK JTDI JTDO DS3106 |
Similar Part No. - DS3106LN |
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Similar Description - DS3106LN |
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