Current DAC

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3

Note 1:

All voltages with respect to ground. Currents entering the IC are specified positive, and currents exiting the IC are negative.

Note 2:

Note 3:

Supply current specified with all outputs set to zero current setting. A0 and A1 are connected to GND. SDA and SCL are con-

Note 4:

The output-voltage range must be satisfied to ensure the device meets its accuracy and linearity specifications.

Note 5:

Temperature drift excludes drift caused by external resistor.

Note 6:

Differential linearity is defined as the difference between the expected incremental current increase with respect to position

and the actual increase. The expected incremental increase is the full-scale range divided by 127.

Note 7:

Guaranteed by design.

Note 8:

Integral linearity is defined as the difference between the expected value as a function of the setting and the actual value.

The expected value is a straight line between the zero and the full-scale values proportional to the setting.

Note 9:

OUTPUT CURRENT SOURCE CHARACTERISTICS (continued)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

DC source

0.32

Output Current Variation Due to

Power-Supply Change

DC sink

0.42

%/V

0.16

Output Current Variation Due to

Output-Voltage Change

0.16

%/V

Output Leakage Current at Zero

Current Setting

-1

+1

μA

Output Current Differential

Linearity

DNL

(Notes 6, 7)

-0.5

+0.5

LSB

Output Current Integral Linearity

INL

(Notes 7, 8)

-1

+1

LSB

AC ELECTRICAL CHARACTERISTICS

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

SCL Clock Frequency

(Note 9)

0

400

kHz

Bus Free Time Between STOP

and START Conditions

1.3

μs

Hold Time (Repeated) START

Condition

0.6

μs

Low Period of SCL

1.3

μs

High Period of SCL

0.6

μs

Data Hold Time

0

0.9

μs

Data Setup Time

100

ns

START Setup Time

0.6

μs

SDA and SCL Rise Time

(Note 10)

300

ns

SDA and SCL Fall Time

(Note 10)

300

ns

STOP Setup Time

0.6

μs

SDA and SCL Capacitive

Loading

(Note 10)

400

pF