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MAX148BMJP Datasheet(PDF) 5 Page - Maxim Integrated Products |
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MAX148BMJP Datasheet(HTML) 5 Page - Maxim Integrated Products |
5 / 23 page +2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs _______________________________________________________________________________________ 5 TIMING CHARACTERISTICS (VDD = +2.7V to +5.25V, TA = TMIN to TMAX, unless otherwise noted.) Note 1: Tested at VDD = 2.7V; COM = 0; unipolar single-ended input mode. Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has been calibrated. Note 3: MAX149—internal reference, offset nulled; MAX148—external reference (VREF = +2.500V), offset nulled. Note 4: Ground “on” channel; sine wave applied to all “off” channels. Note 5: Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. Note 6: The common-mode range for the analog inputs is from AGND to VDD. Note 7: Sample tested to 0.1% AQL. Note 8: External load should not change during conversion for specified accuracy. Note 9: ADC performance is limited by the converter’s noise floor, typically 300FVP-P. Note 10: Guaranteed by design. Not subject to production testing. Note 11: The MAX148 typically draws 400FA less than the values shown. Note 12: Measured as |VFS(2.7V) - VFS(5.25V)|. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Acquisition Time tACQ 1.5 μs DIN to SCLK Setup tDS 100 ns DIN to SCLK Hold tDH 0 ns SCLK Fall to Output Data Valid tDO Figure 1 MAX14_ _C/E 20 200 ns MAX14_ _M 20 240 CS Fall to Output Enable tDV Figure 1 240 ns CS Rise to Output Disable tTR Figure 2 240 ns CS to SCLK Rise Setup tCSS 100 ns CS to SCLK Rise Hold tCSH 0 ns SCLK Pulse Width High tCH 200 ns SCLK Pulse Width Low tCL 200 ns SCLK Fall to SSTRB tSSTRB Figure 1 240 ns CS Fall to SSTRB Output Enable tSDV External clock mode only, Figure 1 240 ns CS Rise to SSTRB Output Disable tSTR External clock mode only, Figure 2 240 ns SSTRB Rise to SCLK Rise tSCK Internal clock mode only (Note 7) 0 ns |
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