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MAX1070 Datasheet(PDF) 8 Page - Maxim Integrated Products |
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MAX1070 Datasheet(HTML) 8 Page - Maxim Integrated Products |
8 / 18 page 1.5Msps, Single-Supply, Low-Power, True-Differential, 10-Bit ADCs 8 _______________________________________________________________________________________ Pin Description PIN NAME FUNCTION 1 AIN- Negative Analog Input 2 REF External Reference Voltage Input. VREF sets the analog input range. Bypass REF with a 0.01µF capacitor and a 4.7µF capacitor to RGND. 3 RGND Reference Ground. Connect RGND to GND. 4VDD Positive Analog Supply Voltage (+2.7V to 3.6V). Bypass VDD with a 0.01µF capacitor and a 10µF capacitor to GND. 5, 11 N.C. No Connection 6 GND Ground. GND is internally connected to EP. 7VL Positive Logic Supply Voltage (1.8V to VDD). Bypass VL with a 0.01µF capacitor and a 10µF capacitor to GND. 8 DOUT Serial Data Output. Data is clocked out on the rising edge of SCLK. 9 CNVST Convert Start. Forcing CNVST high prepares the part for a conversion. Conversion begins on the falling edge of CNVST. The sampling instant is defined by the falling edge of CNVST. 10 SCLK Serial Clock Input. Clocks data out of the serial interface. SCLK also sets the conversion speed. 12 AIN+ Positive Analog Input — EP Exposed Paddle. EP is internally connected to GND. Detailed Description The MAX1070/MAX1071 use an input T/H and succes- sive-approximation register (SAR) circuitry to convert an analog input signal to a digital 10-bit output. The serial interface requires only three digital lines (SCLK, CNVST, and DOUT) and provides easy interfacing to microprocessors (µPs) and DSPs. Figure 3 shows the simplified internal structure for the MAX1070/MAX1071. True-Differential Analog Input T/H The equivalent circuit of Figure 4 shows the input archi- tecture of the MAX1070/MAX1071, which is composed of a T/H, a comparator, and a switched-capacitor digital-to- analog converter (DAC). The T/H enters its tracking mode on the 14th SCLK rising edge of the previous conversion. Upon power-up, the T/H enters its tracking mode immedi- ately. The positive input capacitor is connected to AIN+. The negative input capacitor is connected to AIN-. The T/H enters its hold mode on the falling edge of CNVST and the difference between the sampled positive and negative input voltages is converted. The time required for the T/H to acquire an input signal is determined by how quickly its input capacitance is charged. If the input signal’s source impedance is high, the acquisition time lengthens. The acquisition time, tACQ, is the minimum time needed for the signal to be acquired. It is calculated by the following equation: tACQ ≥ 8 x (RS + RIN) x 16pF where RIN = 200 Ω, and RS is the source impedance of the input signal. Note: tACQ is never less than 125ns, and any source impedance below 12 Ω does not significantly affect the ADC’s AC performance. Input Bandwidth The ADC’s input-tracking circuitry has a 15MHz small- signal bandwidth, making it possible to digitize high- speed transient events and measure periodic signals with bandwidths exceeding the ADC’s sampling rate by using undersampling techniques. To avoid high-fre- quency signals being aliased into the frequency band of interest, anti-alias filtering is recommended. Analog Input Protection Internal protection diodes that clamp the analog input to VDD and GND allow the analog input pins to swing from GND - 0.3V to VDD + 0.3V without damage. Both inputs must not exceed VDD or be lower than GND for accurate conversions. |
Similar Part No. - MAX1070_09 |
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Similar Description - MAX1070_09 |
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