1.8Msps, Single-Supply, Low-Power,

True-Differential, 12-Bit ADCs

4

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Note 1: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and the offset

error have been nulled.

Note 2: No missing codes over temperature.

Note 3: Conversion time is defined as the number of clock cycles (16) multiplied by the clock period.

Note 4: At sample rates below 10ksps, the input full-linear bandwidth is reduced to 5kHz.

Note 5: The listed value of three SCLK cycles is given for full-speed continuous conversions. Acquisition time begins on the 14th ris-

ing edge of SCLK and terminates on the next falling edge of CNST. The IC idles in acquisition mode between conversions.

Note 6: Undersampling at the maximum signal bandwidth requires the minimum jitter spec for SINAD performance.

TIMING CHARACTERISTICS

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

SCLK Pulse-Width High

15.6

ns

SCLK Pulse-Width Low

15.6

ns

14

17

SCLK Rise to DOUT Transition

24

ns

DOUT Remains Valid After SCLK

4ns

CNVST Fall to SCLK Fall

10

ns

CNVST Pulse Width

20

ns

Power-Up Time; Full Power-Down

2ms

Restart Time; Partial Power-Down

16

Cycles

CNVST

SCLK

DOUT

Figure 1. Detailed Serial-Interface Timing

GND

6k

Ω

DOUT

DOUT

GND

6k

Ω

Figure 2. Load Circuits for Enable/Disable Times