WCDMA Quasi-Direct Modulator

with VGA and PA Driver

6

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Pin Description

PIN

NAME

FUNCTION

1

N.C.

Connect to RF GND on PCB

2

POUT

Transmitter Output. This is an open-collector output and requires a pullup inductor to the supply

voltage. This pullup inductor can be part of the output matching network and can be connected

directly to the battery.

Supply for the PA Driver. This pin must be bypassed with a capacitor to system ground as close to

the pin as possible. Do not share the ground vias for the bypass capacitor with any other branch (see

the Typical Operating Circuit).

4

BIAS_SET

Bias-Setting Pin. The DC voltage at this pin is a bandgap voltage. For nominal bias, connect a 12k

Ω

resistor to ground. The value of this resistor can be adjusted to alter current consumption, linearity,

and noise performance of the RF output.

5

VGC

Gain-Control Pin. Analog input pin controls both the IF VGA and RF VGA gain. When not driven, the

voltage on this pin is typically +1.5V. An RC filter on this pin must be used to filter out DAC noise or

the PDM clock.

Supply for IF Section. Bypass to system ground with a capacitor as close to the pin as possible. Do

not share the ground vias for the bypass capacitor with any other branch (see the Typical Operating

Circuit).

Supply for Baseband Section. Bypass to system ground with a capacitor as close to the pin as

possible. Do not share the ground vias for the bypass capacitor with any other branch (see the

Typical Operating Circuit).

8

IDLE

Idle CMOS Digital Input. Drive LOW to place the device in WCDMA compressed mode (VCO and PLL

are ON; all others are OFF). A small RC lowpass filter can be used to minimize the effect of external

digital noise.

9

SHDN

Shutdown CMOS Digital Input. Drive LOW to place the device in shutdown (everything OFF except

serial interface and registers, which retain their values). A small RC lowpass filter can be used to

minimize the effect of external digital noise. A logic-low on the

SHDN pin overrides the serial bus

SHDN bit status.

10, 11

I+, I-

Differential I-Channel Baseband Inputs to the Baseband Filter

12, 13

Q+, Q-

Differential Q-Channel Baseband Inputs to the Baseband Filter

14, 24, 25

N.C.

Leave Open

15

LD

Lock CMOS Output. This pin is an open-drain output. Output HIGH indicates the RF PLL is locked.

16

REF

Reference Frequency Input. This pin is internally biased to approximately +1.0V and must be AC-

coupled to the reference source. This is a high-impedance port and can be externally terminated to

the desired impedance.

17

Supply for PLL. Bypass with a capacitor to GND (see the Typical Operating Circuit).

18

Supply for Synthesizer Charge Pump. Bypass with a capacitor to GND (see the Typical Operating

Circuit).

19

RFCP

RF Charge-Pump Output. Connect the RF PLL’s loop filter between RFCP and system ground. Keep

the line from this pin to the tank tune input as short as possible to prevent spurious pickup. Connect

the loop filter as close to the tune input as possible.