Low-Voltage 8:1 Mux/Dual 4:1 Mux/Triple SPDT/

Quad SPDT in UCSP Package

6

_______________________________________________________________________________________

Note 2: The algebraic convention, where the most negative value is a minimum and the most positive value is a maximum, is used

in this data sheet.

Note 6:

Note 7: Leakage parameters are guaranteed by design.

Note 9: Between any two switches.

Note 10: Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the

specified analog signal ranges.

ELECTRICAL CHARACTERISTICS—Dual ±5V Supplies (continued)

(MAX4691/MAX4692/MAX4693 only)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

+25°C

-2

2

X, Y, Z On-Leakage Current

(Note 7)

V+ = 5.5V; V- = -5.5V;

±4.5V;

±4.5V,

or unconnected

-40°C to +85°C

-20

20

nA

DYNAMIC

+25°C

55

80

Enable Turn-On Time

Ω,

-40°C to +85°C

90

ns

+25°C

35

50

Enable Turn-Off Time

Ω,

-40°C to +85°C

60

ns

+25°C

60

90

Figure 3

-40°C to +85°C

100

ns

+25°C

2

20

Break-Before-Make

Ω,

-40°C to +85°C

2

ns

Charge Injection

Q

+25°C

1.8

pC

Off-Isolation (Note 8)

Ω,

+25°C

-82

dB

Crosstalk (Note 9)

Ω,

+25°C

-84

dB

Total Harmonic Distortion

THD

Ω,

+25°C

0.02

%

DIGITAL I/O

Input Logic-High

2V

Input Logic-Low

0.8

V

Input Leakage Current

-1

+1

µA

SUPPLY

+25°C

0.1

Positive Supply Current

I+

V+ = 5.5V; V- = 5.5V;

-40°C to +85°C

1

µA