MAX8819B datasheet(2/29 Pages) MAXIM

Part #	MAX8819B

Description	PMIC with Integrated Chargers and Smart Power Selector in a 4mm x 4mm TQFN

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Manufacturer	MAXIM [Maxim Integrated Products]

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PMIC with Integrated Chargers and Smart

Power Selector in a 4mm x 4mm TQFN

2

_______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS

(DC, LX_ unconnected; VEP = VGND = 0V, VBAT = 4V, DLIM[1:2] = 00, EN123 = EN4 = low, VFB1 = VFB2 = VFB3 = 1.1V, VFB4 = 0.6V,

PV13 = PV2 = SYS, TA = -40°C to +85°C, capacitors as shown in Figure 1, RCISET = 3kΩ, unless otherwise noted.) (Note 3)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

DC POWER INPUT

DC Voltage Range

VDC

4.1

5.5

V

MAX8819A/MAX8819C

4.3

4.35

4.4

SYS Regulation Voltage

VSYS_REG

VDC = 5.75V

MAX8819B

5.1

5.3

5.5

V

DC Undervoltage Threshold

VUVLO_DC VDC rising, 500mV typical hysteresis

3.95

4.00

4.05

V

DC Overvoltage Threshold

VOVLO_DC VDC rising, 300mV typical hysteresis

5.811

5.9

6.000

V

DLIM[1:2] = 10

90

95

100

DLIM[1:2] = 01

450

475

500

DC Current Limit

(Note 4)

IDCLIM

VDC = 5.75V, VSYS = 5V

for MAX8819B or VSYS =

4V for MAX8819A/

MAX8819C

DLIM[1:2] = 00

900

1000

1100

mA

DLIM[1:2] = 11 (suspend)

0.02

0.035

DLIM[1:2]

≠ 11, ISYS = 0mA, IBAT = 0mA,

EN123 = low, EN4 = low, CEN = high,

VDC = 5.5V

1.33

DC Quiescent Current

IDCIQ

DLIM[1:2]

≠ 11, ISYS = 0mA, EN123 = low,

EN4 = low, CEN = low, VDC = 5.5V

0.95

mA

DC-to-SYS Dropout Resistance

RDS

VDC = 4V, ISYS = 400mA, DLIM[1:2] = 01

0.330

0.700

Ω

DC-to-SYS Soft-Start Time

tSS-D-S

1.5

ms

DC Thermal-Limit Temperature

Die temperature where current limit is

reduced

100

°C

DC Thermal-Limit Gain

Amount of input current reduction above

thermal-limit temperature

5%/

°C

SYSTEM

System Operating Voltage Range

VSYS

2.6

5.5

V

ABSOLUTE MAXIMUM RATINGS

DC, SYS, BAT, CISET, DLIM1, DLIM2, EN123

CEN, EN4, CHG, RST1, FB1, FB2, FB3 to GND....-0.3V to +6V

PV2 to GND ...............................................-0.3V to (VSYS + 0.3V)

PV13 to SYS...........................................................-0.3V to +0.3V

PG1, PG2, PG3, PG4 to GND................................-0.3V to +0.3V

COMP4, FB4 to GND ................................-0.3V to (VSYS + 0.3V)

LX4 to PG4 .............................................................-0.3V to +33V

OVP4 to GND .........................................................-0.3V to +33V

LX1, LX2, LX3 Continuous Current (Note 1) .........................1.5A

LX4 Current ................................................................750mARMS

Output Short-Circuit Duration.....................................Continuous

Continuous Power Dissipation (TA = +70°C)

28-Pin Thin QFN Single-Layer Board (derate 20.8mW/°C

above +70°C)...........................................................1666.7mW

28-Pin Thin QFN Multilayer Board (derate 28.6mW/°C

above +70°C)...........................................................2285.7mW

Junction-to-Case Thermal Resistance (

θJC) (Note 2)

28-Lead Thin QFN...........................................................3°C/W

Operating Temperature Range ...........................-40°C to +85°C

Junction Temperature........................................-40°C to +125°C

Storage Temperature.........................................-65°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

Note 1: LX1, LX2, LX3 have clamp diodes to their respective PG_ and PV_. Applications that forward bias these diodes must take

care not to exceed the package power dissipation limits.

Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer

board. For detailed information on package thermal considerations, refer to http://www.maxim-ic.com/thermal-tutorial.

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