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PI2001-00-QEIG Datasheet(PDF) 8 Page - Vicor Corporation |
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PI2001-00-QEIG Datasheet(HTML) 8 Page - Vicor Corporation |
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8 / 23 page  be {VG-SP = VC - VSP – 0.5V}. Note that VC is the controller internal regulated voltage. When a reverse current fault is initiated, the gate driver pulls the GATE pin low and discharges the FET gate with 4Apeak capability. When the input source voltage is applied and before the MOSFET is fully enhanced, a voltage greater than the Forward Over Current (FOC) Threshold will be present across the MOSFET. To avoid an erroneous FOC detection, a VGS detector blanks the FOC and FWD comparators from initiating a fault, until the GATE pin reaches 77% of VG-CLMP. If VC is too low to establish the Gate Clamp condition the reference for detection is 77% of {VC-V(SP) - 0.25V}. Fault: The fault circuit output is an open collector with 40μs delay to prevent any false triggering. The FT pin will be pulled low when any of the following faults occur: • Reverse current • Forward Over-Current • Forward Low Current • Over-Temperature • Input Under-Voltage • Input Over-Voltage • VC pin Under-Voltage The only fault condition that initiates gate turn-off of the MOSFET (as well as a fault flag signal) is when the reverse current fault conditions are met. All other fault conditions issue only a fault flag signal via the FT pin, but do not affect the gate of the MOSFET. The FT pin serves as an indicator that a fault condition may be present. This information can be reported to a Host to signal that some system level maintenance may be required. Picor Corporation • picorpower.com PI2001 Rev 1.0 Page 8 of 23 |
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