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QPI-11LZ-01 Datasheet(PDF) 4 Page - Vicor Corporation |
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QPI-11LZ-01 Datasheet(HTML) 4 Page - Vicor Corporation |
4 / 5 page Picor Corporation • www.picorpower.com QPI-11 Data Sheet Rev. 1.6 Page 4 of 5 QPI-11 PCB Layout Recommendations Figure 5 – Recommended mounting on a 2 layer board The filtering performance of the QPI-11 and –12 is sensitive to capacitive coupling between its input and output pins. Parasitic plane capacitance must be kept below 1 pico-Farad between inputs and outputs using the layout shown above and the recommendations described below to achieve maximum conducted EMI performance. To avoid capacitive coupling between input and output pins, there should not be any planes or large traces that run under both input and output pins, such as a ground plane or power plane. For example, if there are two signal planes or large traces where one trace runs under the input pins, and the other under the output pins, and both planes over lap in another area, they will cause capacitive coupling between input and output pins. Also, planes that run under both input and outputs pins, but do not cross, can cause capacitive coupling if they are capacitively by-passed together. Figure 5 shows the recommended pcb layout on a 2 layer board. Here, the top layer planes are duplicated on the bottom layer so that there can be no over- lapping of input and output planes. This method can be used for boards of greater layer count. Picor lidded QP SIPs are not hermetically sealed and must not be exposed to liquid, including but not limited to cleaning solvents, aqueous washing solutions or pressurized sprays. When soldering, it is recommended that no-clean flux solder be used, as this will insure that potentially corrosive mobile ions will not remain on, around, or under the module following the soldering process. For applications requiring water wash compatibility the “–01” open frame version should be used. Post Solder Cleaning |
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