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MAX11609 Datasheet(PDF) 10 Page - Maxim Integrated Products |
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MAX11609 Datasheet(HTML) 10 Page - Maxim Integrated Products |
10 / 22 page 2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCs 10 ______________________________________________________________________________________ signal. At the end of the acquisition interval, the T/H switches move to the hold position retaining the charge on CT/H as a stable sample of the input signal. During the conversion interval, the switched capacitive DAC adjusts to restore the comparator input voltage to 0V within the limits of 10-bit resolution. This action requires 10 conversion clock cycles and is equivalent to transferring a charge of 11pF (VIN+ - VIN-) from CT/H to the binary weighted capacitive DAC, forming a digital representation of the analog input signal. Sufficiently low source impedance is required to ensure an accurate sample. A source impedance of up to 1.5k Ω does not significantly degrade sampling accuracy. To minimize sampling errors with higher source impedances, connect a 100pF capacitor from the analog input to GND. This input capacitor forms an RC filter with the source impedance limiting the analog-input bandwidth. For larg- er source impedances, use a buffer amplifier to maintain analog-input signal integrity and bandwidth. When operating in internal clock mode, the T/H circuitry enters its tracking mode on the eighth rising clock edge of the address byte (see the Slave Address section). The T/H circuitry enters hold mode on the falling clock edge of the acknowledge bit of the address byte (the ninth clock pulse). A conversion or a series of conversions is then internally clocked and the MAX11606–MAX11611 holds SCL low. With external clock mode, the T/H circuitry enters track mode after a valid address on the rising edge of the clock during the read (R/W = 1) bit. Hold mode is then entered on the rising edge of the second clock pulse during the shifting out of the first byte of the result. The conversion is performed during the next 10 clock cycles. The time required for the T/H circuitry to acquire an input signal is a function of the input sample capaci- tance. If the analog-input source impedance is high, the acquisition time constant lengthens and more time must be allowed between conversions. The acquisition time (tACQ) is the minimum time needed for the signal to be acquired. It is calculated by: tACQ ≥ 9 (RSOURCE + RIN) CIN where RSOURCE is the analog-input source impedance, RIN = 2.5kΩ, and CIN = 22pF. tACQ is 1.5/fSCL for internal clock mode and tACQ = 2/fSCL for external clock mode. Analog Input Bandwidth The MAX11606–MAX11611 feature input-tracking cir- cuitry with a 5MHz small-signal bandwidth. The 5MHz input bandwidth makes it possible to digitize high- speed transient events and measure periodic signals with bandwidths exceeding the ADC’s sampling rate by using under sampling techniques. To avoid high-fre- quency signals being aliased into the frequency band of interest, anti-alias filtering is recommended. Analog Input Range and Protection Internal protection diodes clamp the analog input to VDD and GND. These diodes allow the analog inputs to CT/H CT/H TRACK AIN0 AIN1 AIN2 AIN3/REF GND ANALOG INPUT MUX CAPACITIVE DAC REF CAPACITIVE DAC REF MAX11606 MAX11607 HOLD TRACK HOLD VDD/2 Figure 4. Equivalent Input Circuit |
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Similar Description - MAX11609 |
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