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MAX16056 Datasheet(PDF) 3 Page - Maxim Integrated Products |
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MAX16056 Datasheet(HTML) 3 Page - Maxim Integrated Products |
3 / 16 page 125nA Supervisory Circuits with Capacitor- Adjustable Reset and Watchdog Timeouts _______________________________________________________________________________________ 3 Note 2: Devices are production tested at TA = +25°C. Specifications over temperature limits are guaranteed by design. Note 3: WDI input period is 1s with tRISE and tFALL < 50ns. Note 4: Guaranteed by design, not production tested. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS TA = -40°C to +125°C 197 240 282 SRT Ramp Current IRAMP1 VSRT = 0V to VRAMP1, VCC = 1.6V to 5V TA = +25°C 210 240 270 nA SRT Ramp Threshold VRAMP1 VCC = 1.6V to 5V (VRAMP rising) 1.173 1.235 1.297 V TA = +25°C 5 6.4 8 Watchdog Timeout Clock Period tWDPER TA = -40°C to +125°C 3.5 6.4 9.5 ms TA = -40°C to +125°C 197 240 282 SWT Ramp Current IRAMP2 VSWT = 0V to VRAMP2, VCC = 1.6V to 5V TA = +25°C 210 240 270 nA SWT Ramp Threshold VRAMP2 VCC = 1.6V to 5V (VRAMP2 rising) 1.173 1.235 1.297 V VCC ≥ 1.0V, ISINK = 50µA 0.3 VCC ≥ 2.7V, ISINK = 1.2mA 0.3 VOL VCC ≥ 4.5V, ISINK = 3.2mA 0.4 VCC ≥ 1.8V, ISOURCE = 200µA 0.8 x VCC VCC ≥ 2.25V, ISOURCE = 500µA 0.8 x VCC RESET Output Voltage VOH MAX16056/MAX16057 VCC ≥ 4.5V, ISOURCE = 800µA 0.8 x VCC V RESET Output-Leakage Current, Open Drain ILKG VCC > VTH, reset not asserted, VRESET = 5.5V (MAX16058/MAX16059) 1.0 µA VIH 0.7 x VCC Input-Logic Levels VIL 0.3 x VCC V MR Minimum Pulse Width tMPW 1µs MR Glitch Rejection 200 ns MR to RESET Delay tMRD 250 ns WDI Minimum Pulse Width (Note 4) 150 ns Input Leakage Current MR, WDI, WDS is connected to GND or VCC -100 +100 nA ELECTRICAL CHARACTERISTICS (continued) (VCC = 1.2V to 5.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = 3.3V, TA = +25°C.) (Note 2) |
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