Low-Voltage, Quad-/Hex-/Octal-Voltage

µP Supervisors

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7

Pin Description (MAX16000/MAX16001/MAX16002)

PIN

NAME

FUNCTION

1

1

1

IN3

Monitored Input Voltage 3. See Table 1 for the input voltage threshold.

2

2

2

IN4

Monitored Input Voltage 4. See Table 1 for the input voltage threshold.

3

4

4

GND

Ground

45

5

Unmonitored Power-Supply Input

5

6

—

OUT3

Output 3. When the voltage at IN3 falls below its threshold, OUT3 goes low and stays low until the

6

7

—

OUT4

Output 4. When the voltage at IN4 falls below its threshold, OUT4 goes low and stays low until the

710

8

MARGIN

Active-Low Manual Deassert Input. Pull MARGIN low to deassert all outputs (go into high state),

regardless of the voltage at any monitored input.

8

11

—

OUT2

Output 2. When the voltage at IN2 falls below its threshold, OUT2 goes low and stays low until the

9

12

—

OUT1

Output 1. When the voltage at IN1 falls below its threshold, OUT1 goes low and stays low until the

10

14

10

IN1

Monitored Input Voltage 1. See Table 1 for the input voltage threshold.

11

15

11

IN2

Monitored Input Voltage 2. See Table 1 for the input voltage threshold.

12

16

12

TOL

Threshold Tolerance Input. Connect TOL to GND to select 5% threshold tolerance. Connect TOL

—

3

3

WDI

Watchdog Timer Input. If WDI remains low or high for longer than the watchdog timeout period,

RESET is asserted. The timer clears whenever a reset is asserted or a rising or falling edge on

WDI is detected. The watchdog timer enters a startup period that allows 54s for the first

transition to occur before a reset. Leave WDI unconnected to disable the watchdog timer. The

WDI floating-state detector uses a small 400nA current. Therefore, do not connect WDI to

anything that will source or sink more than 200nA. Note that the leakage current specification for

most three-state drivers exceeds 200nA.

—8

6

MR

Active-Low Manual Reset Input. Pull MR low to assert RESET low. RESET remains low for the

Ω resistor.

—

9

7

SRT

Set Reset Timeout Input. Connect a capacitor from SRT to GND to set the reset timeout period.

The reset timeout period can be calculated as follows:

—13

9

RESET

Active-Low Reset Output. RESET asserts low when any of the monitored voltages falls below its

respective threshold or MR is asserted. RESET remains asserted for the reset timeout period

after all monitored voltages exceed their respective thresholds and MR is deasserted. This

open-drain output has a 30µA internal pullup.

——

—

EP

Exposed Pad. EP is internally connected to GND. Connect EP to the ground plane to provide a

low thermal resistance path from the IC junction to the PCB. Do not use as the electrical

connection to GND.