High-Voltage Watchdog Timers with

Adjustable Timeout Delay

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9

Detailed Description

The MAX16997/MAX16998 are µP supervisory circuits

for high-input-voltage and low-quiescent-current appli-

cations. These devices improve system reliability by

monitoring the sub-system for software code execution

errors. The MAX16997A/MAX16998A/B/D detect down-

stream circuit failures, and provide switchover to

redundant circuitry. These devices provide complete

adjustability for reset and watchdog functions.

The MAX16998A/B/D generate two output signals,

RESET and ENABLE, that depend on the voltage level

at RESETIN and the signal at WDI. RESET asserts

whenever RESETIN drops below the selected reset

threshold voltage. RESET remains low for the reset

timeout period after all reset conditions are deasserted,

and then goes high. RESET also asserts for a period of

generates one output signal (ENABLE) based on the

voltage level at EN and the signal at WDI.

The MAX16997A/MAX16998A provide watchdog time-

out adjustability with an external capacitor. The

MAX16998A asserts RESET when two consecutive WDI

falling edges do not occur within the watchdog timeout

period. This device also asserts ENABLE if three con-

secutive watchdog timeout periods have elapsed with-

out a falling edge at WDI. ENABLE remains low until

three consecutive good WDI falling edges occur.

ENABLE does not assert if the voltage at RESETIN (EN)

is below its threshold. For the MAX16997A, the watch-

dog timer starts timing if the voltage at EN is higher

than a preset threshold level. Each time the voltage at

EN rises from below to above the preset threshold volt-

age, the initial watchdog timeout period is 8 times the

described above, the MAX16997A behaves the same

as the MAX16998A.

The MAX16998B/MAX16998D contain a window watch-

dog timer that looks for activity outside an expected

window of operation. The window size is factory-set to

50% (MAX16998B) or 75% (MAX16998D) of the adjust-

ed watchdog timeout period.

Reset Output (

RESET) (MAX16998A/B/D)

The reset output is typically connected to the reset

input of the µC to start or restart it in a known state. The

MAX16998A/B/D provide an active-low open-drain

reset logic to prevent code execution errors.

For the MAX16998A/B/D, RESET asserts whenever

RESETIN drops below the selected reset threshold volt-

period after RESETIN exceeds the selected threshold

voltage, and then goes high.

when two consecutive WDI falling edges do not occur

within the adjusted watchdog timeout period. The

when a WDI falling edge does not occur within the

open window period.

Anytime reset asserts, the watchdog timer clears. At

the end of the reset timeout period, RESET goes high,

and the watchdog timer is restarted from zero (see the

Selecting the Watchdog Timeout Capacitor section).

Enable Output (

ENABLE)

If the µC fails to operate correctly (e.g., the software

execution is stuck in a loop), WDI does not trigger any

more and RESET pulls low, resetting the µC. If the µC

does not work properly in the next loop either, the

device asserts RESET again. After three watchdog

timeout periods elapse with no falling edges at WDI,

ENABLE asserts and flags a backup circuit that can

take over the operation.

ENABLE remains low until three consecutive WDI

falling edges with periods shorter than the watchdog

timeout occur. ENABLE does not assert if the voltage at

RESETIN (EN) is below its threshold. These devices are

guaranteed to be in correct ENABLE output logic state

Power-On/Power-Off Sequence

Figure 5 shows the power-up and power-down

sequence

for

RESET and ENABLE for the

MAX16998A/B/D.

logic-low. As RESETIN rises, RESET remains low. When

RESET remains low. When the reset timeout period

ends, RESET goes high.

1.1V. Figure 6 shows the detailed power-up sequence

for the MAX16998A/B/D.