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F25L08PA-100PAIG Datasheet(PDF) 10 Page - Elite Semiconductor Memory Technology Inc.

Part # F25L08PA-100PAIG
Description  3V Only 8 Mbit Serial Flash Memory with Dual
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Manufacturer  ESMT [Elite Semiconductor Memory Technology Inc.]
Direct Link  http://www.esmt.com.tw/index.asp
Logo ESMT - Elite Semiconductor Memory Technology Inc.

F25L08PA-100PAIG Datasheet(HTML) 10 Page - Elite Semiconductor Memory Technology Inc.

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ESMT
F25L08PA
Operation Temperature Condition -40°C~85°C
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2009
Revision: 1.3
10/32
CE
SCK
SI
0 1 2 3 4 5 6 7 8
1516
2324
3132
39 40
4748
55 56
63 64
80
N+4
DOUT
N+3
DOUT
N+2
DOUT
N+1
DOUT
N
DOUT
MSB
MSB
MSB
HIGH IMPENANCE
SO
0B
ADD.
ADD.
ADD.
MODE3
MODE0
71 72
X
Note : X = Dummy Byte : 8 Clocks Input Dummy (VIL or VIH)
Read (33MHz)
The Read instruction supports up to 33 MHz, it outputs the data
starting from the specified address location. The data output
stream is continuous through all addresses until terminated by a
low to high transition on CE . The internal address pointer will
automatically increment until the highest memory address is
reached. Once the highest memory address is reached, the
address pointer will automatically increment to the beginning
(wrap-around) of the address space, i.e. for 8Mbit density, once
the data from address location FFFFFH had been read, the next
output will be from address location 000000H.
The Read instruction is initiated by executing an 8-bit command,
03H, followed by address bits [A23 -A0]. CE must remain active
low for the duration of the Read cycle. See Figure 2 for the Read
sequence.
Figure 2: Read Sequence
Fast Read (50 MHz; 100 MHz)
The Fast Read instruction supporting up to 100 MHz is initiated
by executing an 8-bit command, 0BH, followed by address bits
[A23 -A0] and a dummy byte. CE must remain active low for the
duration of the Fast Read cycle. See Figure 3 for the Fast Read
sequence.
Following a dummy byte (8 clocks input dummy cycle), the Fast
Read instruction outputs the data starting from the specified
address location. The data output stream is continuous through
all addresses until terminated by a low to high transition on CE .
The internal address pointer will automatically increment until the
highest memory address is reached. Once the highest memory
address is reached, the address pointer will automatically
increment to the beginning (wrap-around) of the address space,
i.e. for 8Mbit density, once the data from address location
FFFFFH has been read, the next output will be from address
location 000000H.
Figure 3: Fast Read Sequence


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