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F25L16PA-100PG Datasheet(PDF) 6 Page - Elite Semiconductor Memory Technology Inc. |
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F25L16PA-100PG Datasheet(HTML) 6 Page - Elite Semiconductor Memory Technology Inc. |
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6 / 33 page  ESMT F25L16PA Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.4 6/33 Table 1: F25L16PA Sector Address Table – continued II Block Address Block Sector Sector Size (Kbytes) Address range A20 A19 A18 A17 A16 95 4KB 05F000H – 05FFFFH : : : 5 80 4KB 050000H – 050FFFH 0 0 1 0 1 79 4KB 04F000H – 04FFFFH : : : 4 64 4KB 040000H – 040FFFH 0 0 1 0 0 63 4KB 03F000H – 03FFFFH : : : 3 48 4KB 030000H – 030FFFH 0 0 0 1 1 47 4KB 02F000H – 02FFFFH : : : 2 32 4KB 020000H – 020FFFH 0 0 0 1 0 31 4KB 01F000H – 01FFFFH : : : 1 16 4KB 010000H – 010FFFH 0 0 0 0 1 15 4KB 00F000H – 00FFFFH : : : 0 0 4KB 000000H – 000FFFH 0 0 0 0 0 STATUS REGISTER The software status register provides status on whether the flash memory array is available for any Read or Write operation, whether the device is Write enabled, and the state of the memory Write protection. During an internal Erase or Program operation, the status register may be read only to determine the completion of an operation in progress. Table 2 describes the function of each bit in the software status register. Table 2: Software Status Register Bit Name Function Default at Power-up Read/Write 0 BUSY 1 = Internal Write operation is in progress 0 = No internal Write operation is in progress 0 R 1 WEL 1 = Device is memory Write enabled 0 = Device is not memory Write enabled 0 R 2 BP0 Indicate current level of block write protection (See Table 3) 1 R/W 3 BP1 Indicate current level of block write protection (See Table 3) 1 R/W 4 BP2 Indicate current level of block write protection (See Table 3) 1 R/W 5 RESERVED Reserved for future use 0 N/A 6 AAI Auto Address Increment Programming status 1 = AAI programming mode 0 = Page Program mode 0 R 7 BPL 1 = BP2,BP1,BP0 are read-only bits 0 = BP2,BP1,BP0 are read/writable 0 R/W Note: 1. Only BP0, BP1, BP2 and BPL are writable. 2. All register bits are volatility 3. All area are protected at power-on (BP2=BP1=BP0=1) |
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