ESMT

M12L32321A

Elite Semiconductor Memory Technology Inc.

Publication Date : Oct. 2008

Revision : 1.1

11/28

*Note:

1. All inputs expect CKE & DQM can be don’t care when CS is high at the CLK high going edge.

2. Bank active & read/write are controlled by BA.

BA

Active & Read/Write

0

Bank A

1

Bank B

3.Enable and disable auto precharge function are controlled by A10/AP in read/write command.

A10/AP

BA

Operation

0

Disable auto precharge, leave bank A active at end of burst.

0

1

Disable auto precharge, leave bank B active at end of burst.

0

Enable auto precharge, precharge bank A at end of burst.

1

1

Enable auto precharge, precharge bank B at end of burst.

4.A10/AP and BA control bank precharge when precharge command is asserted.

A10/AP

BA

precharge

0

0

Bank A

0

1

Bank B

1

X

Both Banks