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M12L64164A-7TA Datasheet(PDF) 9 Page - Elite Semiconductor Memory Technology Inc. |
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M12L64164A-7TA Datasheet(HTML) 9 Page - Elite Semiconductor Memory Technology Inc. |
9 / 44 page ESMT M12L64164A Operation temperature condition -25℃ ~ 85℃ Elite Semiconductor Memory Technology Inc. Publication Date: Dec. 2004 Revision: 0.1 9/44 makes Hi-Z state the data-out of 2 CLK cycles after.(Read DQM latency is 2) MODE REGISTER FIELD TABLE TO PROGRAM MODES Register Programmed with MRS Address A13~A12 A11~A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Function RFU RFU RFU TM CAS Latency BT Burst Length Test Mode CAS Latency Burst Type Burst Length A8 A7 Type A6 A5 A4 Latency A3 Type A2 A1 A0 BT = 0 BT = 1 0 0 Mode Register Set 0 0 0 Reserved 0 Sequential 0 0 0 1 1 0 1 Reserved 0 0 1 Reserved 1 Interleave 0 0 1 2 2 1 0 Reserved 0 1 0 2 0 1 0 4 4 1 1 Reserved 0 1 1 3 0 1 1 8 8 1 0 0 Reserved 1 0 0 Reserved Reserved 1 0 1 Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved 1 1 0 Reserved Reserved 1 1 1 Reserved 1 1 1 Full Page Reserved Full Page Length : 256 POWER UP SEQUENCE 1.Apply power and start clock, Attempt to maintain CKE = ”H”, DQM = ”H” and the other pin are NOP condition at the inputs. 2. Maintain stable power , stable clock and NOP input condition for a minimum of 200us. 3. Issue precharge commands for all banks of the devices. 4. Issue 2 or more auto-refresh commands. 5. Issue mode register set command to initialize the mode register. cf.) Sequence of 4 & 5 is regardless of the order. The device is now ready for normal operation. Note : 1. RFU(Reserved for future use) should stay “0” during MRS cycle. |
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