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CS2000-CP Datasheet(PDF) 3 Page - Cirrus Logic |
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CS2000-CP Datasheet(HTML) 3 Page - Cirrus Logic |
3 / 36 page CS2000-CP DS761F1 3 8.3.3 Auxiliary Output Source Selection (AuxOutSrc[1:0]) ............................................................. 29 8.3.4 Enable Device Configuration Registers 1 (EnDevCfg1) ........................................................ 30 8.4 Device Configuration 2 (Address 04h) ........................................................................................... 30 8.4.1 Lock Clock Ratio (LockClk[1:0]) ............................................................................................ 30 8.4.2 Fractional-N Source for Frequency Synthesizer (FracNSrc) ................................................. 30 8.5 Global Configuration (Address 05h) ............................................................................................... 30 8.5.1 Device Configuration Freeze (Freeze) ................................................................................ 30 8.5.2 Enable Device Configuration Registers 2 (EnDevCfg2) ....................................................... 31 8.6 Ratio 0 - 3 (Address 06h - 15h) ...................................................................................................... 31 8.7 Function Configuration 1 (Address 16h) ........................................................................................ 31 8.7.1 Clock Skip Enable (ClkSkipEn) ............................................................................................. 31 8.7.2 AUX PLL Lock Output Configuration (AuxLockCfg) .............................................................. 32 8.7.3 Reference Clock Input Divider (RefClkDiv[1:0]) .................................................................... 32 8.8 Function Configuration 2 (Address 17h) ........................................................................................ 32 8.8.1 Enable PLL Clock Output on Unlock (ClkOutUnl) ................................................................. 32 8.8.2 Low-Frequency Ratio Configuration (LFRatioCfg) ................................................................ 32 8.9 Function Configuration 3 (Address 1Eh) ........................................................................................ 33 8.9.1 Clock Input Bandwidth (ClkIn_BW[2:0]) ................................................................................ 33 9. CALCULATING THE USER DEFINED RATIO .................................................................................... 34 9.1 High Resolution 12.20 Format ....................................................................................................... 34 9.2 High Multiplication 20.12 Format ................................................................................................... 34 10. PACKAGE DIMENSIONS .................................................................................................................. 35 THERMAL CHARACTERISTICS ......................................................................................................... 35 11. ORDERING INFORMATION .............................................................................................................. 36 12. REFERENCES .................................................................................................................................... 36 13. REVISION HISTORY .......................................................................................................................... 36 LIST OF FIGURES Figure 1. Typical Connection Diagram ........................................................................................................ 6 Figure 2. CLK_IN Sinusoidal Jitter Tolerance ............................................................................................. 9 Figure 3. CLK_IN Sinusoidal Jitter Transfer ................................................................................................ 9 Figure 4. CLK_IN Random Jitter Rejection and Tolerance .........................................................................9 Figure 5. Control Port Timing - I²C Format ................................................................................................ 10 Figure 6. Control Port Timing - SPI Format (Write Only) .......................................................................... 11 Figure 7. Delta-Sigma Fractional-N Frequency Synthesizer ..................................................................... 12 Figure 8. Hybrid Analog-Digital PLL .......................................................................................................... 13 Figure 9. Fractional-N Source Selection Overview ................................................................................... 13 Figure 10. Internal Timing Reference Clock Divider ................................................................................. 14 Figure 11. REF_CLK Frequency vs a Fixed CLK_OUT ............................................................................ 14 Figure 12. External Component Requirements for Crystal Circuit ............................................................ 15 Figure 13. CLK_IN removed for > 223 SysClk cycles ................................................................................ 16 Figure 14. CLK_IN removed for < 223 SysClk cycles but > tCS .................................................................................. 16 Figure 15. CLK_IN removed for < tCS .................................................................................................................................. 17 Figure 16. Low bandwidth and new clock domain .................................................................................... 18 Figure 17. High bandwidth with CLK_IN domain re-use ........................................................................... 18 Figure 18. Ratio Feature Summary ........................................................................................................... 22 Figure 19. PLL Clock Output Options ....................................................................................................... 23 Figure 20. Auxiliary Output Selection ........................................................................................................ 23 Figure 21. Control Port Timing in SPI Mode ............................................................................................. 25 Figure 22. Control Port Timing, I²C Write .................................................................................................. 26 Figure 23. Control Port Timing, I²C Aborted Write + Read .......................................................................26 |
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