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CDK2000-CLK Datasheet(PDF) 3 Page - Cirrus Logic |
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CDK2000-CLK Datasheet(HTML) 3 Page - Cirrus Logic |
3 / 26 page CS2100-OTP DS841F1 3 9. PACKAGE DIMENSIONS .................................................................................................................... 25 THERMAL CHARACTERISTICS ......................................................................................................... 25 10. ORDERING INFORMATION .............................................................................................................. 26 11. REVISION HISTORY .......................................................................................................................... 26 LIST OF FIGURES Figure 1. Typical Connection Diagram ........................................................................................................ 5 Figure 2. CLK_IN Sinusoidal Jitter Tolerance ............................................................................................. 8 Figure 3. CLK_IN Sinusoidal Jitter Transfer ................................................................................................ 8 Figure 4. CLK_IN Random Jitter Rejection and Tolerance .........................................................................8 Figure 5. Delta-Sigma Fractional-N Frequency Synthesizer .......................................................................9 Figure 6. Hybrid Analog-Digital PLL .......................................................................................................... 10 Figure 7. Internal Timing Reference Clock Divider ................................................................................... 11 Figure 8. REF_CLK Frequency vs a Fixed CLK_OUT .............................................................................. 12 Figure 9. External Component Requirements for Crystal Circuit .............................................................. 12 Figure 10. Low bandwidth and new clock domain .................................................................................... 13 Figure 11. High bandwidth with CLK_IN domain re-use ........................................................................... 13 Figure 12. Ratio Feature Summary ........................................................................................................... 16 Figure 13. PLL Clock Output Options ....................................................................................................... 16 Figure 14. Auxiliary Output Selection ........................................................................................................ 17 Figure 15. M2 Mapping Options ................................................................................................................ 18 Figure 16. Parameter Configuration Sets .................................................................................................. 20 LIST OF TABLES Table 1. Modal and Global Configuration .................................................................................................. 11 Table 2. Ratio Modifier .............................................................................................................................. 15 Table 3. Example 12.20 R-Values ............................................................................................................ 23 Table 4. Example 20.12 R-Values ............................................................................................................ 23 |
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