Electronic Components Datasheet Search
Selected language     English  ▼


CS61577_09 Datasheet(PDF) 11 Page - Cirrus Logic

Part No. CS61577_09
Description  T1/E1 Line Interface
Download  30 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  CIRRUS [Cirrus Logic]
Homepage  http://www.cirrus.com
Logo 

 11 page
background image
Transmit All Ones Select
The transmitter provides for all ones insertion at
the frequency of TCLK. Transmit all ones is se-
lected when TAOS goes high, and causes
continuous ones to be transmitted on the line
(TTIP and TRING). In this mode, the TPOS and
TNEG (or TDATA) inputs are ignored. If Remote
Loopback is in effect, any TAOS request will be
ignored.
Receiver
The receiver extracts data and clock from an AMI
(Alternate Mark Inversion) coded signal and out-
puts clock and synchronized data. The receiver is
sensitive to signals over the entire range of
ABAM cable lengths and requires no equalization
or ALBO (Automatic Line Build Out) circuits.
The signal is received on both ends of a center-
tapped, center-grounded transformer. The
transformer is center tapped on the IC side. The
clock and data recovery circuit exceeds the jitter
tolerance specifications of Publications 43802,
43801, AT&T 62411, TR-TSY-000170, and
CCITT REC. G.823.
A block diagram of the receiver is shown in Fig-
ure 10. The two leads of the transformer (RTIP
and RRING) have opposite polarity allowing the
receiver to treat RTIP and RRING as unipolar sig-
nals. Comparators are used to detect pulses on
RTIP and RRING. The comparator thresholds are
dynamically established at a percent of the peak
level (50% of peak for E1, 65% of peak for T1;
with the slicing level selected by LEN2/1/0 in-
puts).
The leading edge of an incoming data pulse trig-
gers the clock phase selector. The phase selector
chooses one of the 13 available phases which the
delay line produces for each bit period. The out-
269 ns
244 ns
194 ns
219 ns
488 ns
Nominal Pulse
0
10
50
80
90
100
110
120
-10
-20
Percent of
nominal
peak
voltage
Figure 9. Mask of the Pulse at the 2048 kbps Interface
For c oax ia l c abl e,
75
Ω
l oad
and
transformer specified
in Application Section.
For shielded twisted
pair, 120
Ω load and
transformer specified
in Application Section.
Nominal peak voltage of a mark (pulse)
2.37 V
3 V
Peak voltage of a space (no pulse)
0
±0.237 V
0
±0.30 V
Nominal pulse width
244 ns
Ratio of the amplitudes of positive and negative
pulses at the center of the pulse interval
0.95 to 1.05*
Ratio of the widths of positive and negative
pulses at the nominal half amplitude
0.95 to 1.05*
* When configured with a 0.47
μF nonpolarized capacitor in series with the TX transformer
primary as shown in Figures A1, A2 and A3.
Table 4. CCITT G.703 Specifications
CS61577
DS155F
11




Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30 


Datasheet Download




Link URL

Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Bookmark   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com 2003 - 2017    


Mirror Sites
English : Alldatasheet.com  , Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp  |   Russian : Alldatasheetru.com
Korean : Alldatasheet.co.kr   |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com  |   Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl