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AS4DDR264M72PBG1 Datasheet(PDF) 5 Page - Austin Semiconductor

Part # AS4DDR264M72PBG1
Description  64Mx72 DDR2 SDRAM w/ SHARED CONTROL BUS iNTEGRATED Plastic Encapsulated Microcircuit
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Manufacturer  AUSTIN [Austin Semiconductor]
Direct Link  http://www.austinsemiconductor.com
Logo AUSTIN - Austin Semiconductor

AS4DDR264M72PBG1 Datasheet(HTML) 5 Page - Austin Semiconductor

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background image
iiiiiPEM
PEM
PEM
PEM
PEM
4.8 G
4.8 G
4.8 G
4.8 G
4.8 Gbbbbb SDRAM-DDR2
SDRAM-DDR2
SDRAM-DDR2
SDRAM-DDR2
SDRAM-DDR2
AS4DDR264M72PBG1
AS4DDR264M72PBG1
Rev. 3.0 6/09
Austin Semiconductor, Inc. ● Austin, Texas ● 512.339.1188 ● www.austinsemiconductor.com
5
Austin Semiconductor, Inc.
FIGURE 4 - POWER-UP AND INITIALIZATION
Notes appear on page 7
LV
CMOS
LOW LEVEL
2
t VTD1
CKE
RTT
Power-up:
VDD an
d stable
clo ck (CK, CK#)
T = 200µs (MIN)
Hi
gh-Z
DM
15
DQ
S
15
Hi
gh-Z
A
ddress
3
CK
CK#
tCL
VTT1
VREF
VDDQ
Comman d
3
NOP4
PRE
T0
Ta0
Don
’t care
tCL
tCK
ODT
DQ
15
Hi
gh-Z
T = 400ns
(MIN) 16
T
b0
200
cycles of CK are re quire d before a READ comman d can be issued.
MR with
DLL RE
SET
t RFC
LM8
PRE9
LM7
REF10
REF
LM11
T
g0
Th0
Ti0
Tj0
MR without
DLL RE
SET
EMR with
O
CD default
Tk0
Tl0
Tm0
Te0
Tf0
EMR(2)
EMR(3)
t MRD
LM6
LM5
A10 = 1
t RPA
T
c0Td0
SSTL_18
LOW LEVEL
2
Vali
d16
Vali
d
In
dicates a break in
time s
cale
LM12
EMR with
O
CD exit
LM13
Normal
operation
See note 17
Code
Code
A10 = 1
Code
Code
Code
Code
Code
t MRD
t MRD
t MRD
t MRD
t RPA
t RFC
t MRD
t MRD
EMR
VDD
VDDL


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