AS5SP128K36DQ

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Revision 1.0 03/22/04

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6

COTS PEM

AS5SP128K36DQ

Austin Semiconductor, Inc.

SSRAM

TA= Min. and Max temperatures of Screening level chosen)

-26 [250Mhz]

-30 [200Mhz]

-35 [166Mhz]

-40 [133Mhz]

Parameter

Symbol

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Units

Notes

Clock (CLK) Cycle Time

tCYC

4.00

-

5.00

-

6.00

-

7.50

-

ns

Clock (CLK) High Time

tCH

1.70

-

2.00

-

2.50

-

3.00

-

ns

1

Clock (CLK) Low Time

tCL

1.70

-

2.00

-

2.50

-

3.00

-

ns

1

Clock Access Time

tCD

-

2.60

3.00

3.50

4.00

ns

2

Clock (CLK) High to Output Low-Z

tCLZ

1.25

-

1.25

-

1.25

-

1.25

-

ns

2,3,4,5

Clock High to Output High-Z

tCHZ

1.25

2.60

1.25

3.00

1.25

3.50

1.25

3.50

ns

2,3,4,5

Output Enable to Data Valid

tOE

-

2.60

-

3.00

-

3.50

-

4.00

ns

6

Output Hold from Clock High

tOH

1.25

-

1.25

-

1.25

-

1.25

-

ns

Output Enable Low to Output Low-Z

tOELZ

0.00

-

0.00

-

0.00

-

0.00

-

ns

2,3,4,5

Output Enable High to Output High-Z

tOEHZ

-

2.60

-

3.00

-

3.50

-

3.50

ns

2,3,4,5

Address Set-up to CLK High

tAS

1.00

1.30

1.50

1.50

ns

7,8

Address Hold from CLK High

tAH

0.50

0.50

0.50

0.50

ns

7,8

Address Status Set-up to CLK High

tASS

1.00

1.30

1.50

1.50

ns

7,8

Address Status Hold from CLK High

tASH

0.50

0.50

0.50

0.50

ns

7,8

Address Advance Set-up to CLK High

tADVS

1.00

1.30

1.50

1.50

ns

7,8

Address Advance Hold from CLK High

tADVH

0.50

0.50

0.50

0.50

ns

7,8

Chip Enable Set-up to CLK High (CEx\, CE2)

tCES

1.00

1.30

1.50

1.50

ns

7,8

Chip Enable Hold from CLK High (CEx\, CE2)

tCEH

0.50

0.50

0.50

0.50

ns

7,8

Data Set-up to CLK High

tDS

1.00

1.30

1.50

1.50

ns

7,8

Data Hold from CLK High

tDH

0.50

0.50

0.50

0.50

ns

7,8

Write Set-up to CLK High (GW\, BWE\, BWx\)

tWES

1.00

1.30

1.50

1.50

ns

7,8

Write Hold from CLK High (GW\, BWE\, BWX\)

tWEH

0.50

0.50

0.50

0.50

ns

7,8

ZZ High to Power Down

tPD

2

2

2

2

cycles

ZZ Low to Power Up

tPU

2

2

2

2

cycles

Notes to Switching Specifications:

1.

Measured as HIGH when above VIH and Low when below VIL

2.

This parameter is measured with the output loading shown in AC Test Loads

3.

This parameter is sampled

4.

Transition is measured +500mV from steady state voltage

5.

Critical specification(s) when Design Considerations are being reviewed/analyized for Bus Contentention

6.

OE\ is a Don't Care when a Byte or Global Write is sampled LOW

7.

A READ cycle is defined by Byte or Global Writes sampled LOW and ADSP\ is sampled HIGH for the required SET-UP and HOLD times

8.

This is a Synchronous device. All addresses must meet the specified SET-UP and HOLD times for all rising edges of CLK when either

ADSP\ or ADSC\ is sampled LOW while the device is enabled. All other synchronous inputs must meet the SET-UP and HOLD times

with stable logic levels for all rising edges of clock (CLK) during device operation (enabled). Chip Enable (Cex\, CE2) must be valid

at each rising edge of clock (CLK) when either ADSP\ or ADSC\ is LOW to remain enabled.