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AS5SS256K36 Datasheet(PDF) 9 Page - Austin Semiconductor |
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AS5SS256K36 Datasheet(HTML) 9 Page - Austin Semiconductor |
9 / 16 page SSRAM SSRAM SSRAM SSRAM SSRAM AS5SS256K36 & AS5SS256K36A AS5SS256K36 & AS5SS256K36A Rev. 3.6 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 9 Austin Semiconductor, Inc. ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Note 1) (-55oC to +125oC or -40oC to +85oC) MIN MAX MIN MAX CLOCK Clock cycle time tKC 10.0 15.0 ns Clock frequency tKF 100 66 MHz Clock HIGH time tKH 3.0 4.0 ns 2 Clock LOW time tKL 3.0 4.0 ns 2 OUTPUT TIMES Clock to output valid tKQ 8.5 10.0 ns Clock to output invalid tKQX 3.0 3.0 ns 3 Clock to output in Low-Z tKQLZ 3.0 3.0 ns 3, 4, 5, 6, Clock to output in High-Z tKQHZ 5.0 5.0 ns 3, 4, 5, 6, OE\ to output valid tOEQ 5.0 5.0 ns 7 OE\ to output in Low-Z tOELZ 0 0 ns 3, 4, 5, 6, OE\ to output in High-Z tOEHZ 5.0 5.0 ns 3, 4, 5, 6, SETUP TIMES Address tAS 1.8 2.0 ns 8, 9 Address status (ADSC\, ADSP\) tADSS 1.8 2.0 ns 8, 9 Address advance (ADV\) tAAS 1.8 2.0 ns 8, 9 Byte write enables (BWa\ - BWd\, GW\, BWE\) tWS 1.8 2.0 ns 8, 9 Data-in tDS 1.8 2.0 ns 8, 9 Chip enable (CE\) tCES 1.8 2.0 ns 8, 9 HOLD TIMES Address tAH 0.5 0.5 ns 8, 9 Address status (ADSC\, ADSP\) tADSH 0.5 0.5 ns 8, 9 Address advance (ADV\) tAAH 0.5 0.5 ns 8, 9 Byte write enables (BWa\ - BWd\, GW\, BWE\) tWH 0.5 0.5 ns 8, 9 Data-in tDH 0.5 0.5 ns 8, 9 Chip enable (CE\) tCEH 0.5 0.5 ns 8, 9 UNITS NOTES SYMBOL DESCRIPTION -10 -8.5 NOTE: 1. Test conditions as specified with the output loading shown in Figure 1 unless otherwise noted. 2. Measured as HIGH above V IH and LOW below V IL . 3. This parameter is measured with the output loading shown in Figure 2 for 3.3V I/O. 4. This parameter is sampled. 5. Transition is measured +500mV from steady state voltage. 6. Refer to Technical Note TN-58-09, “Synchronous SRAM Bus Contention Design Considerations,” for a more thorough discussion on these parameters. 7. OE\ is a “Don’t Care” when a byte write enable is sampled LOW. 8. A READ cycle is defined by byte write enables all HIGH or ADSP\ LOW for the required setup and hold times. A WRITE cycle is defined by a t least one byte write enable LOW and ADSP\ HIGH for the required setup and hold times. 9. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK when either ADSP\ or ADSC\ is LOW and chip enabled. All other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each rising edge of CLK when either ADSP\ or ADSC\ is LOW to remain enabled. |
Similar Part No. - AS5SS256K36_05 |
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Similar Description - AS5SS256K36_05 |
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