SSRAM

SSRAM

SSRAM

SSRAM

SSRAM

AS5SS256K36 &

AS5SS256K36A

AS5SS256K36 &

AS5SS256K36A

Rev. 3.6 06/05

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

9

Austin Semiconductor, Inc.

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS

MIN

MAX

MIN

MAX

CLOCK

Clock cycle time

10.0

15.0

ns

Clock frequency

100

66

MHz

Clock HIGH time

3.0

4.0

ns

2

Clock LOW time

3.0

4.0

ns

2

OUTPUT TIMES

Clock to output valid

8.5

10.0

ns

Clock to output invalid

3.0

3.0

ns

3

Clock to output in Low-Z

3.0

3.0

ns

3, 4, 5, 6,

Clock to output in High-Z

5.0

5.0

ns

3, 4, 5, 6,

OE\ to output valid

5.0

5.0

ns

7

OE\ to output in Low-Z

0

0

ns

3, 4, 5, 6,

OE\ to output in High-Z

5.0

5.0

ns

3, 4, 5, 6,

SETUP TIMES

Address

1.8

2.0

ns

8, 9

Address status (ADSC\, ADSP\)

1.8

2.0

ns

8, 9

Address advance (ADV\)

1.8

2.0

ns

8, 9

Byte write enables (BWa\ - BWd\, GW\, BWE\)

1.8

2.0

ns

8, 9

Data-in

1.8

2.0

ns

8, 9

Chip enable (CE\)

1.8

2.0

ns

8, 9

HOLD TIMES

Address

0.5

0.5

ns

8, 9

Address status (ADSC\, ADSP\)

0.5

0.5

ns

8, 9

Address advance (ADV\)

0.5

0.5

ns

8, 9

Byte write enables (BWa\ - BWd\, GW\, BWE\)

0.5

0.5

ns

8, 9

Data-in

0.5

0.5

ns

8, 9

Chip enable (CE\)

0.5

0.5

ns

8, 9

UNITS

NOTES

SYMBOL

DESCRIPTION

-10

-8.5

NOTE:

1. Test conditions as specified with the output loading shown in Figure 1 unless otherwise noted.

2. Measured as HIGH above V

IH

and LOW below V

IL

.

3. This parameter is measured with the output loading shown in Figure 2 for 3.3V I/O.

4. This parameter is sampled.

5. Transition is measured +500mV from steady state voltage.

6. Refer to Technical Note TN-58-09, “Synchronous SRAM Bus Contention Design Considerations,” for a more thorough discussion on these

parameters.

7. OE\ is a “Don’t Care” when a byte write enable is sampled LOW.

8. A READ cycle is defined by byte write enables all HIGH or ADSP\ LOW for the required setup and hold times. A WRITE cycle is defined by

a t

least one byte write enable LOW and ADSP\ HIGH for the required setup and hold times.

9. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK when either ADSP\ or

ADSC\ is LOW and chip enabled. All other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges

of clock (CLK) when the chip is enabled. Chip enable must be valid at each rising edge of CLK when either ADSP\ or ADSC\ is LOW to

remain enabled.