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AS29LV016J Datasheet(PDF) 7 Page - Austin Semiconductor |
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AS29LV016J Datasheet(HTML) 7 Page - Austin Semiconductor |
7 / 40 page CO CO CO CO COTS PEM TS PEM TS PEM TS PEM TS PEM BOO BOO BOO BOO BOOT SECT T SECT T SECT T SECT T SECTOR FLASH OR FLASH OR FLASH OR FLASH OR FLASH AS29LV016J AS29LV016J Rev. 0.0 02/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 7 Austin Semiconductor, Inc. REQUIREMENTS FOR READING ARRAY DATA WRITING COMMANDS / COMMAND SEQUENCES To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to V IL, and OE# to VIH. For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. See Word Byte Configuration on page 6 for more information. The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. Word Byte Program Command Sequence on page 18 has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sectors, or the entire device. Table 2 on page 9 and Table 3 on page 10 indicate the address space that each sector occupies. A “sector address” consists of the address bits required to uniquely select a sector. The Command Definitions on page 17 has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to Autoselect Mode on page 11 and Autoselect Command Sequence on page 17 for more information. I CC2 in the DC Characteristics table represents the active current specification for the write mode. AC Characteristics on page 29 contains timing specification tables and timing diagrams for write operations. PROGRAM AND ERASE OPERATION STATUS During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7–DQ0. Standard read cycle timings and I CC read specifications apply. Refer to Write Operation Status on page 22 for more information, and to AC Characteristics on page 29 for timing diagrams. To read array data from the outputs, the system must drive the CE# and OE# pins to V IL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at V IH. The BYTE# pin determines whether the device outputs array data in words or bytes. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See Reading Array Data on page 17 for more information. Refer to the AC Read Operations on page 29 for timing specifications and to Figure 12, on page 29 for the timing diagram. I CC1 in the DC Characteristics table represents the active current specification for reading array data. |
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