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AD5422 Datasheet(PDF) 11 Page - Analog Devices |
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AD5422 Datasheet(HTML) 11 Page - Analog Devices |
11 / 40 page AD5412/AD5422 Rev. A | Page 11 of 40 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 12 11 DVCC FAULT GND LATCH CLEAR CLEAR SELECT AVSS SCLK SDIN GND GND SDO 20 21 22 23 24 19 18 17 16 15 14 13 –VSENSE +VSENSE VOUT NC NOTES 1. NC = NO CONNECT 2. THE PADDLE CAN BE CONNECTED TO 0V IF THE OUTPUT VOLTAGE RANGE IS UNIPOLAR. THE PADDLE CAN BE LEFT ELECTRICALLY UNCONNECTED PROVIDED THAT A SUPPLY CONNECTION IS MADE AT THE AVSS PIN. IT IS RECOMMENDED THAT THE PADDLE BE THERMALLY CONNECTED TO A COPPER PLANE FOR ENHANCED THERMAL PERFORMANCE. IOUT BOOST CCOMP DVCC SELECT RSET REFOUT REFIN AVDD AD5412/ AD5422 TOP VIEW (Not to Scale) NOTES 1. NC = NO CONNECT. 2. THE EXPOSED PADDLE CAN BE CONNECTED TO 0V IF THE OUTPUT VOLTAGE RANGE IS UNIPOLAR. THE EXPOSED PADDLE CAN BE LEFT ELECTRICALLY UNCONNECTED PROVIDED THAT A SUPPLY CONNECTION IS MADE AT THE AVSS PIN. IT IS RECOMMENDED THAT THE PADDLE BE THERMALLY CONNECTED TO A COPPER PLANE FOR ENHANCED THERMAL PERFORMANCE. PIN 1 INDICATOR 1 NC 2 FAULT 3 GND 4 CLEAR SELECT 5 CLEAR 6 LATCH 7 SCLK 8 SDIN 9 SDO 10 NC 23 DVCC SELECT 24 CCOMP 25 NC 26 IOUT 27 BOOST 28 CAP1 29 CAP2 30 NC 22 NC 21 NC TOP VIEW (Not to Scale) AD5412/AD5422 Figure 5. TSSOP Pin Configuration Figure 6. LFCSP Pin Configuration Table 6. Pin Function Descriptions Pin No. Mnemonic Description TSSOP LFCSP 1 14, 37 AVSS Negative Analog Supply Pin. Voltage ranges from –3 V to –24 V. This pin can be connected to 0 V if the output voltage range is unipolar. 2 39 DVCC Digital Supply Pin. Voltage ranges from 2.7 V to 5.5 V. 3 2 FAULT Fault Alert. This pin is asserted low when an open circuit is detected in current mode or an overtemperature is detected. Open drain output must be connected to a pull-up resistor. 4, 12 3, 15 GND These pins must be connected to 0 V. 18 1, 10, 11, 19, 20, 21, 22, 25, 30, 31, 35, 38, 40 NC No Connection. Do not connect to these pins. 5 4 CLEAR SELECT Selects the voltage output clear value, either zero-scale or midscale code (see Table 21). 6 5 CLEAR Active High Input. Asserting this pin sets the current output to the bottom of the selected range or sets the voltage output to the user selected value (zero-scale or midscale). 7 6 LATCH Positive Edge Sensitive Latch. A rising LATCH edge parallel loads the input shift register data into the DAC register, also updating the output. 8 7 SCLK Serial Clock Input. Data is clocked into the shift register on the rising edge of SCLK. This operates at clock speeds of up to 30 MHz. 9 8 SDIN Serial Data Input. Data must be valid on the rising edge of SCLK. 10 9 SDO Serial Data Output. Used to clock data from the serial register in daisy-chain or readback mode. Data is valid on the rising edge of SCLK (see Figure 3 and Figure 4). 11 12, 13 GND Ground Reference Pin. 13 16 RSET An external, precision, low drift 15 kΩ current setting resistor can be connected to this pin to improve the IOUT temperature drift performance. See the AD5412/AD5422 Features section. 14 17 REFOUT Internal Reference Voltage Output. REFOUT = 5 V ± 2 mV. 15 18 REFIN External Reference Voltage Input. Reference input range is 4 V to 5 V. REFIN = 5 V for a specified performance. |
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