ADCLK954BCPZ-REEL7 datasheet(6/12 Pages) AD

Part #	ADCLK954BCPZ-REEL7

Description	Two Selectable Inputs, 12 LVPECL Outputs, SiGe Clock Fanout Buffer

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Manufacturer	AD [Analog Devices]

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ADCLK954

Rev. A | Page 6 of 12

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

NOTES

1. EPAD MUST BE SOLDERED TO VEE POWER PLANE.

1

IN_SEL

2

CLK0

3

CLK0

4

VREF0

5

VT0

6

CLK1

7

CLK1

8

VT1

9

VREF1

10

VEE

23 Q7

24 Q6

25 Q6

26 Q5

27 Q5

28 Q4

29 Q4

30 VCC

22 Q7

21 VCC

TOP VIEW

(Not to Scale)

ADCLK954

Figure 2. Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

IN_SEL

Input Select. Logic 0 selects CLK0 and CLK0 inputs. Logic 1 selects CLK1 and CLK1 inputs.

2

CLK0

Differential Input (Positive) 0.

3

CLK0

Differential Input (Negative) 0.

4

VREF0

Reference Voltage. Reference voltage for biasing ac-coupled CLK0 and CLK0 inputs.

5

VT0

Center Tap. Center tap of a 100 Ω input resistor for CLK0 and CLK0 inputs.

6

CLK1

Differential Input (Positive) 1.

7

CLK1

Differential Input (Negative) 1.

8

VT1

Center Tap. Center tap of a 100 Ω input resistor for CLK1 and CLK1 inputs.

9

VREF1

Reference Voltage. Reference voltage for biasing ac-coupled CLK1 and CLK1 inputs.

10

VEE

Negative Supply Pin.

11, 20, 21,

30, 31, 40

VCC

Positive Supply Pin.

12, 13

Q11, Q11

Differential LVPECL Outputs.

14, 15

Q10, Q10

Differential LVPECL Outputs.

16, 17

Q9, Q9

Differential LVPECL Outputs.

18, 19

Q8, Q8

Differential LVPECL Outputs.

22, 23

Q7, Q7

Differential LVPECL Outputs.

24, 25

Q6, Q6

Differential LVPECL Outputs.

26, 27

Q5, Q5

Differential LVPECL Outputs.

28, 29

Q4, Q4

Differential LVPECL Outputs.

32, 33

Q3, Q3

Differential LVPECL Outputs.

34, 35

Q2, Q2

Differential LVPECL Outputs.

36, 37

Q1, Q1

Differential LVPECL Outputs.

38, 39

Q0, Q0

Differential LVPECL Outputs.

(41)

EPAD

EPAD must be connected to VEE.

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