ADN4666ARUZ datasheet(4/12 Pages) AD

Part #	ADN4666ARUZ

Description	3 V, LVDS, Quad CMOS Differential Line Receiver

Download	12 Pages

Scroll/Zoom	100%

Manufacturer	AD [Analog Devices]

Direct Link	http://www.analog.com

Logo

4 / 12 page

ADN4666

Rev. 0 | Page 4 of 12

TIMING SPECIFICATIONS

VCC = 3.0 V to 3.6 V, CL = 15 pF to GND, all specifications TMIN to TMAX, unless otherwise noted.1

Table 2.

Parameter2

Symbol

Min

Typ3

Max

Unit

Test Conditions/Comments4, 5

AC CHARACTERISTICS

Differential Propagation Delay, High to Low

tPHLD

1.8

3.3

ns

CL = 15 pF, VID = 300 mV (see Figure 2 and Figure 3)

Differential Propagation Delay, Low to High

tPLHD

1.8

3.3

ns

CL = 15 pF, VID = 300 mV (see Figure 2 and Figure 3)

Differential Pulse Skew6 |tPHLD − tPLHD|

tSKD1

0

0.1

0.35

ns

CL = 15 pF, VID = 300 mV (see Figure 2 and Figure 3)

Differential Channel-to-Channel Skew

(Same Device)7

tSKD2

0

0.1

0.5

ns

CL = 15 pF, VID = 300 mV (see Figure 2 and Figure 3)

Differential Part-to-Part Skew8

tSKD3

1.0

ns

CL = 15 pF, VID = 300 mV (see Figure 2 and Figure 3)

Differential Part-to-Part Skew9

tSKD4

1.5

ns

CL = 15 pF, VID = 300 mV (see Figure 2 and Figure 3)

Rise Time

tTLH

0.35

1.2

ns

CL = 15 pF, VID = 300 mV (see Figure 2 and Figure 3)

Fall Time

tTHL

0.35

1.2

ns

CL = 15 pF, VID = 300 mV (see Figure 2 and Figure 3)

Disable Time, High to Z

tPHZ

8

12

ns

RL = 2 kΩ, CL = 15 pF (see Figure 4 and Figure 5)

Disable Time, Low to Z

tPLZ

8

12

ns

RL = 2 kΩ, CL = 15 pF (see Figure 4 and Figure 5)

Enable Time, Z to High

tPZH

11

17

ns

RL = 2 kΩ, CL = 15 pF (see Figure 4 and Figure 5)

Enable Time, Z to Low

tPZL

11

17

ns

RL = 2 kΩ, CL = 15 pF (see Figure 4 and Figure 5)

Maximum Operating Frequency10

fMAX

200

250

MHz

All channels switching

SIGNAL

GENERATOR

RECEIVER

IS ENABLED

1 Generator waveform for all tests, unless otherwise specified: f = 1 MHz, ZO = 50 Ω, tTLH and tTHL (0% to 100%)

≤ 3 ns for R

INx+

/RINx−.

2 AC parameters are guaranteed by design and characterization.

3 All typical values are given for VCC = 3.3 V and TA = 25°C.

4 Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground, unless otherwise specified.

5 CL includes load and jig capacitance.

6 tSKD1 is the magnitude difference in the differential propagation delay time between the positive-going edge and the negative-going edge of the same channel.

7 Channel-to-channel skew, tSKD2, is defined as the difference between the propagation delay of one channel and that of the others on the same chip with any event on

the inputs.

8 tSKD3 part-to-part skew is the differential channel-to-channel skew of any event between devices. The tSKD3 specification applies to devices at the same VCC and within

5°C of each other within the operating temperature range.

9 tSKD4 part-to-part skew is the differential channel-to-channel skew of any event between devices. The tSKD4 specification applies to devices over the recommended

operating temperature and voltage ranges and across process distribution. tSKD4 is defined as |maximum − minimum| differential propagation delay.

10 fMAX generator input conditions: f = 200 MHz, tTLH = tTHL < 1 ns (0% to 100%), 50% duty cycle, differential (1.05 V to 1.35 V p-p). fMAX generator output criteria: 60%/40%

duty cycle, VOL (maximum = 0.4 V), VOH (minimum = 2.7 V), and load = 15 pF (stray plus probes).

Test Circuits and Timing Diagrams

V

RINx+

RINx–

CL

NOTES

1. CL = LOAD AND TEST JIG CAPACITANCE.

CC

ROUTx

50

Ω

50

Ω

Figure 2. Test Circuit for Receiver Propagation Delay and Transition Time

Similar Part No. - ADN4666ARUZ

Manufacturer	Part #	Datasheet	Description
Analog Devices	ADN4666	593Kb / 12P	LVDS and M-LVDS Circuit Implementation Guide REV. 0

More results

Similar Description - ADN4666ARUZ

Manufacturer	Part #	Datasheet	Description
Analog Devices	ADN4668ARZ	286Kb / 12P	3 V LVDS Quad CMOS Differential Line Receiver REV. A
	ADN4668	306Kb / 12P	3 V LVDS Quad CMOS Differential Line Receiver REV. 0
	ADN4668	286Kb / 12P	3 V LVDS Quad CMOS Differential Line Receiver Rev. A
Texas Instruments	DS90LV048A	1Mb / 22P	[Old version datasheet] 3-V LVDS Quad CMOS Differential Line Receiver
National Semiconductor ...	MNDS90C032-X-RH	281Kb / 10P	LVDS Quad CMOS Differential Line Receiver
Texas Instruments	DS90C032QML	722Kb / 19P	[Old version datasheet] LVDS Quad CMOS Differential Line Receiver
Texas Instruments	DS90C032B	1Mb / 16P	[Old version datasheet] LVDS Quad CMOS Differential Line Receiver
National Semiconductor ...	DS90C032	352Kb / 12P	LVDS Quad CMOS Differential Line Receiver
	DS90C032	231Kb / 12P	LVDS Quad CMOS Differential Line Receiver
	DS90C032B	160Kb / 9P	LVDS Quad CMOS Differential Line Receiver

More results

ADN4666ARUZ Datasheet(PDF) 4 Page - Analog Devices

ADN4666ARUZ Datasheet(HTML) 4 Page - Analog Devices

Similar Part No. - ADN4666ARUZ

Similar Description - ADN4666ARUZ

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12

Datasheet Download

Link URL