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XRT75VL00D Datasheet(PDF) 6 Page - Exar Corporation |
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XRT75VL00D Datasheet(HTML) 6 Page - Exar Corporation |
6 / 92 page XRT75VL00D 3 E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.4 9.2.1 HOW DS3 DATA IS MAPPED INTO SONET ...................................................................................... 49 A Brief Description of an STS-1 Frame 49 Figure 31. A Simple Illustration of the SONET STS-1 Frame ......................................................................... 50 Figure 32. A Simple Illustration of the STS-1 Frame Structure with the TOH and the Envelope Capacity Bytes Designated .................................................................................................................................... 51 Figure 33. The Byte-Format of the TOH within an STS-1 Frame .................................................................... 52 Figure 34. The Byte-Format of the TOH within an STS-1 Frame .................................................................... 53 Figure 35. Illustration of the Byte Structure of the STS-1 SPE ....................................................................... 54 Mapping DS3 data into an STS-1 SPE 54 Figure 36. An Illustration of Telcordia GR-253-CORE's Recommendation on how map DS3 data into an STS-1 SPE ............................................................................................................................................... 55 Figure 37. A Simplified "Bit-Oriented" Version of Telcordia GR-253-CORE's Recommendation on how to map DS3 data into an STS-1 SPE ........................................................................................................ 55 9.2.2 DS3 Frequency Offsets and the Use of the "Stuff Opportunity" Bits ............................................ 56 The Ideal Case for Mapping DS3 data into an STS-1 Signal (e.g., with no Frequency Offsets) 57 Figure 38. A Simple Illustration of a DS3 Data-Stream being Mapped into an STS-1 SPE, via a PTE .......... 57 The 44.736Mbps + 1ppm Case 58 Figure 39. An Illustration of the STS-1 SPE traffic that will be generated by the "Source" PTE, when mapping in a DS3 signal that has a bit rate of 44.736Mbps + 1ppm, into an STS-1 signal ............................ 58 The 44.736Mbps - 1ppm Case 59 Figure 40. An Illustration of the STS-1 SPE traffic that will be generated by the Source PTE, when mapping a DS3 signal that has a bit rate of 44.736Mbps - 1ppm, into an STS-1 signal ................................ 60 9.3 JITTER/WANDER DUE TO POINTER ADJUSTMENTS ............................................................................................ 60 9.3.1 The Concept of an STS-1 SPE Pointer ............................................................................................. 60 Figure 41. An Illustration of an STS-1 SPE straddling across two consecutive STS-1 frames ....................... 61 Figure 42. The Bit-format of the 16-Bit Word (consisting of the H1 and H2 bytes) with the 10 bits, reflecting the location of the J1 byte, designated ............................................................................................... 62 Figure 43. The Relationship between the Contents of the "Pointer Bits" (e.g., the 10-bit expression within the H1 and H2 bytes) and the Location of the J1 Byte within the Envelope Capacity of an STS-1 Frame ... 62 9.3.2 Pointer Adjustments within the SONET Network ............................................................................ 62 9.3.3 Causes of Pointer Adjustments ........................................................................................................ 63 Figure 44. An Illustration of an STS-1 signal being processed via a Slip Buffer ............................................. 64 Figure 45. An Illustration of the Bit Format within the 16-bit word (consisting of the H1 and H2 bytes) with the "I" bits designated .............................................................................................................................. 65 Figure 46. An Illustration of the Bit-Format within the 16-bit word (consisting of the H1 and H2 bytes) with the "D" bits designated ........................................................................................................................ 66 9.3.4 Why are we talking about Pointer Adjustments? ............................................................................ 67 9.4 CLOCK GAPPING JITTER ................................................................................................................................... 67 Figure 47. Illustration of the Typical Applications for the LIU in a SONET De-Sync Application .................... 67 9.5 A REVIEW OF THE CATEGORY I INTRINSIC JITTER REQUIREMENTS (PER TELCORDIA GR-253-CORE) FOR DS3 AP- PLICATIONS .......................................................................................................................................................................... 68 TABLE 18: SUMMARY OF "CATEGORY I INTRINSIC JITTER REQUIREMENT PER TELCORDIA GR-253-CORE, FOR DS3 APPLICATIONS ..................................................................................................................................... 68 9.5.1 DS3 De-Mapping Jitter ....................................................................................................................... 69 9.5.2 Single Pointer Adjustment ................................................................................................................ 69 Figure 48. Illustration of Single Pointer Adjustment Scenario ......................................................................... 69 9.5.3 Pointer Burst ...................................................................................................................................... 69 Figure 49. Illustration of Burst of Pointer Adjustment Scenario ....................................................................... 70 9.5.4 Phase Transients ............................................................................................................................... 70 Figure 50. Illustration of "Phase-Transient" Pointer Adjustment Scenario ...................................................... 70 9.5.5 87-3 Pattern ......................................................................................................................................... 71 Figure 51. An Illustration of the 87-3 Continuous Pointer Adjustment Pattern ................................................ 71 9.5.6 87-3 Add .............................................................................................................................................. 71 Figure 52. Illustration of the 87-3 Add Pointer Adjustment Pattern ................................................................. 72 9.5.7 87-3 Cancel ......................................................................................................................................... 72 |
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