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XRT86VL38IB Datasheet(PDF) 4 Page - Exar Corporation |
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XRT86VL38IB Datasheet(HTML) 4 Page - Exar Corporation |
4 / 154 page XRT86VL3X I T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION REV. 1.2.3 LIST OF PARAGRAPHS 1.0 GENERAL DESCRIPTION AND INTERFACE .........................................................................................4 1.1 PHYSICAL INTERFACE ...................................................................................................................................... 4 1.2 R3 TECHNOLOGY (RELAYLESS / RECONFIGURABLE / REDUNDANCY) .................................................... 5 1.2.1 LINE CARD REDUNDANCY ........................................................................................................................................... 5 1.2.2 TYPICAL REDUNDANCY SCHEMES ............................................................................................................................ 5 1.2.3 1:1 AND 1+1 REDUNDANCY WITHOUT RELAYS ........................................................................................................ 5 1.2.4 TRANSMIT INTERFACE WITH 1:1 AND 1+1 REDUNDANCY ...................................................................................... 5 1.2.5 RECEIVE INTERFACE WITH 1:1 AND 1+1 REDUNDANCY ......................................................................................... 6 1.3 POWER FAILURE PROTECTION ....................................................................................................................... 7 1.4 OVERVOLTAGE AND OVERCURRENT PROTECTION .................................................................................... 7 1.5 NON-INTRUSIVE MONITORING ......................................................................................................................... 7 1.6 T1/E1 SERIAL PCM INTERFACE ....................................................................................................................... 8 1.7 T1/E1 FRACTIONAL INTERFACE ...................................................................................................................... 9 1.8 T1/E1 TIME SLOT SUBSTITUTION AND CONTROL ....................................................................................... 10 1.9 ROBBED BIT SIGNALING/CAS SIGNALING ................................................................................................... 11 1.10 OVERHEAD INTERFACE ................................................................................................................................ 12 1.11 FRAMER BYPASS MODE ............................................................................................................................... 14 1.12 HIGH-SPEED NON-MULTIPLEXED INTERFACE .......................................................................................... 15 1.13 HIGH-SPEED MULTIPLEXED INTERFACE ................................................................................................... 16 2.0 LOOPBACK MODES OF OPERATION .................................................................................................17 2.1 LIU PHYSICAL INTERFACE LOOPBACK DIAGNOSTICS .............................................................................. 17 2.1.1 LOCAL ANALOG LOOPBACK .................................................................................................................................... 17 2.1.2 REMOTE LOOPBACK .................................................................................................................................................. 17 2.1.3 DIGITAL LOOPBACK ................................................................................................................................................... 18 2.1.4 DUAL LOOPBACK ....................................................................................................................................................... 18 2.1.5 FRAMER REMOTE LINE LOOPBACK ........................................................................................................................ 19 2.1.6 FRAMER LOCAL LOOPBACK ..................................................................................................................................... 19 3.0 HDLC CONTROLLERS AND LAPD MESSAGES .................................................................................20 3.1 STORING AND RETRIEVING MESSAGE CONTENTS .................................................................................... 21 3.2 PROGRAMMING SEQUENCE FOR SENDING HDLC MESSAGES ................................................................ 22 3.3 PROGRAMMING SEQUENCE FOR RECEIVING LAPD MESSAGES ............................................................. 23 3.4 RECEIVE HDLC EVENT TIMING ...................................................................................................................... 24 3.5 SS7 (SIGNALING SYSTEM NUMBER 7) FOR ESF IN DS1 ONLY .................................................................. 24 3.6 DS1/E1 DATALINK TRANSMISSION USING THE HDLC CONTROLLERS ................................................... 25 3.7 TRANSMIT BOS (BIT ORIENTED SIGNALING) PROCESSOR ....................................................................... 25 3.7.1 DESCRIPTION OF BOS ................................................................................................................................................ 25 3.7.2 PRIORITY CODEWORD MESSAGE ............................................................................................................................ 25 3.7.3 COMMAND AND RESPONSE INFORMATION ............................................................................................................ 25 3.8 TRANSMIT MOS (MESSAGE ORIENTED SIGNALING) PROCESSOR .......................................................... 26 3.8.1 DISCUSSION OF MOS ................................................................................................................................................. 26 3.8.2 PERIODIC PERFORMANCE REPORT ........................................................................................................................ 27 3.8.3 TRANSMISSION-ERROR EVENT ................................................................................................................................ 27 3.8.4 PATH AND TEST SIGNAL IDENTIFICATION MESSAGE ........................................................................................... 28 3.8.5 FRAME STRUCTURE ................................................................................................................................................... 28 3.8.6 FLAG SEQUENCE ........................................................................................................................................................ 28 3.8.7 ADDRESS FIELD .......................................................................................................................................................... 28 3.8.8 ADDRESS FIELD EXTENSION BIT (EA) ..................................................................................................................... 28 3.8.9 COMMAND OR RESPONSE BIT (C/R) ........................................................................................................................ 28 3.8.10 SERVICE ACCESS POINT IDENTIFIER (SAPI) ........................................................................................................ 29 3.8.11 TERMINAL ENDPOINT IDENTIFIER (TEI) ................................................................................................................. 29 3.8.12 CONTROL FIELD ........................................................................................................................................................ 29 3.8.13 FRAME CHECK SEQUENCE (FCS) FIELD ............................................................................................................... 29 3.8.14 TRANSPARENCY (ZERO STUFFING) ....................................................................................................................... 29 3.9 TRANSMIT SLC®96 DATA LINK CONTROLLER ............................................................................................ 30 3.10 D/E TIME SLOT TRANSMIT HDLC CONTROLLER BLOCK V5.1 OR V5.2 INTERFACE ............................ 31 3.11 AUTOMATIC PERFORMANCE REPORT (APR) ............................................................................................ 31 3.11.1 BIT VALUE INTERPRETATION ................................................................................................................................. 31 4.0 OVERHEAD INTERFACE BLOCK ........................................................................................................33 4.1 DS1 TRANSMIT OVERHEAD INPUT INTERFACE BLOCK ............................................................................. 33 4.1.1 DESCRIPTION OF THE DS1 TRANSMIT OVERHEAD INPUT INTERFACE BLOCK ................................................ 33 |
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