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XRT86VL38IB484 Datasheet(PDF) 7 Page - Exar Corporation

Part # XRT86VL38IB484
Description  T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION
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Manufacturer  EXAR [Exar Corporation]
Direct Link  http://www.exar.com
Logo EXAR - Exar Corporation

XRT86VL38IB484 Datasheet(HTML) 7 Page - Exar Corporation

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XRT86VL3X
IV
REV. 1.2.3
T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION
LIST OF FIGURES
Figure 1.: XRT86VL3x N-Channel DS1 (T1/E1/J1) Framer/LIU Combo ........................................................................... 1
Figure 2.: LIU Transmit Connection Diagram Using Internal Termination ......................................................................... 4
Figure 3.: LIU Receive Connection Diagram Using Internal Termination ......................................................................... 4
Figure 4.: Simplified Block Diagram of the Transmit Interface for 1:1 and 1+1 Redundancy ............................................ 5
Figure 5.: Simplified Block Diagram of the Receive Interface for 1:1 and 1+1 Redundancy ............................................. 6
Figure 6.: Simplified Block Diagram of a Non-Intrusive Monitoring Application ................................................................. 7
Figure 7.: Transmit T1/E1 Serial PCM Interface ................................................................................................................ 8
Figure 8.: Receive T1/E1 Serial PCM Interface ................................................................................................................. 8
Figure 9.: T1 Fractional Interface ....................................................................................................................................... 9
Figure 10.: T1/E1 Time Slot Substitution and Control ..................................................................................................... 10
Figure 11.: Robbed Bit Signaling / CAS Signaling ........................................................................................................... 11
Figure 12.: ESF / CAS External Signaling Bus ................................................................................................................ 11
Figure 13.: SF / SLC-96 or 4-code Signaling in ESF / CAS External Signaling Bus ....................................................... 12
Figure 14.: T1/E1 Overhead Interface ............................................................................................................................. 12
Figure 15.: T1 External Overhead Datalink Bus .............................................................................................................. 13
Figure 16.: E1 Overhead External Datalink Bus .............................................................................................................. 13
Figure 17.: Simplified Block Diagram of the Framer Bypass Mode ................................................................................. 14
Figure 18.: T1 High-Speed Non-Multiplexed Interface .................................................................................................... 15
Figure 19.: E1 High-Speed Non-Multiplexed Interface .................................................................................................... 15
Figure 20.: Transmit High-Speed Bit Multiplexed Block Diagram .................................................................................... 16
Figure 21.: Receive High-Speed Bit Multiplexed Block Diagram ..................................................................................... 16
Figure 22.: Simplified Block Diagram of Local Analog Loopback .................................................................................... 17
Figure 23.: Simplified Block Diagram of Remote Loopback ............................................................................................ 17
Figure 24.: Simplified Block Diagram of Digital Loopback ............................................................................................... 18
Figure 25.: Simplified Block Diagram of Dual Loopback .................................................................................................. 18
Figure 26.: Simplified Block Diagram of the Framer Remote Line Loopback .................................................................. 19
Figure 27.: Simplified Block Diagram of the Framer Local Loopback .............................................................................. 19
Figure 28.: HDLC Controllers .......................................................................................................................................... 20
Figure 29.: Storing and Retrieving Message Contents .................................................................................................... 21
Figure 30.: Sending HDLC Messages ............................................................................................................................. 22
Figure 31.: Receiving HDLC Messages ........................................................................................................................... 23
Figure 32.: Receive HDLC Event Timing ......................................................................................................................... 24
Figure 33.: LAPD Frame Structure .................................................................................................................................. 27
Figure 34.: Block Diagram of the DS1 Transmit Overhead Input Interface of the XRT86VL3x ....................................... 33
Figure 35.: DS1 Transmit Overhead Input Interface Timing in ESF Framing Format mode ............................................ 35
Figure 36.: DS1 Transmit Overhead Input Timing in N or SLC®96 Framing Format Mode ............................................ 36
Figure 37.: DS1 Transmit Overhead Input Interface module in T1DM Framing Format mode ........................................ 36
Figure 38.: Block Diagram of the DS1 Receive Overhead Output Interface of XRT86VL3x ........................................... 37
Figure 39.: DS1 Receive Overhead Output Interface module in ESF framing format mode ........................................... 39
Figure 40.: DS1 Receive Overhead Output Interface Timing in N or SLC®96 Framing Format mode ........................... 40
Figure 41.: DS1 Receive Overhead Output Interface Timing in T1DM Framing Format mode ....................................... 41
Figure 42.: Block Diagram of the E1 Transmit Overhead Input Interface of XRT86VL3x ................................................ 42
Figure 43.: E1 Transmit Overhead Input Interface Timing ............................................................................................... 44
Figure 44.: Block Diagram of the E1 Receive Overhead Output Interface of XRT86VL3x .............................................. 45
Figure 45.: E1 Receive Overhead Output Interface Timing ............................................................................................. 46
Figure 46.: TAOS (Transmit All Ones) ............................................................................................................................. 47
Figure 47.: Simplified Block Diagram of the ATAOS Function ......................................................................................... 47
Figure 48.: Network Loop Up Code Generation .............................................................................................................. 48
Figure 49.: Network Loop Down Code Generation .......................................................................................................... 48
Figure 50.: Long Haul Line Build Out with -7.5dB Attenuation ........................................................................................ 49
Figure 51.: Long Haul Line Build Out with -15dB Attenuation ......................................................................................... 49
Figure 52.: Long Haul Line Build Out with -22.5dB Attenuation ...................................................................................... 50
Figure 53.: Arbitrary Pulse Segment Assignment ............................................................................................................ 51
Figure 54.: Typical Connection Diagram Using Internal Termination .............................................................................. 52
Figure 55.: Typical Connection Diagram Using Internal Termination ............................................................................. 53
Figure 56.: Simplified Block Diagram of the Equalizer and Peak Detector ...................................................................... 54
Figure 57.: Simplified Block Diagram of the Cable Loss Indicator ................................................................................... 54
Figure 58.: Test Configuration for Measuring Receive Sensitivity ................................................................................... 55


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