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XRT86VL30IV80 Datasheet(PDF) 10 Page - Exar Corporation |
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XRT86VL30IV80 Datasheet(HTML) 10 Page - Exar Corporation |
10 / 62 page XRT86VL30 8 T1/E1/J1 BITS ELEMENT - HARDWARE MANUAL REV. 1.0.3 TxSERCLK/ TxLINECLK 54 29 I/O 12 Transmit Serial Clock (TxSERCLK)/Transmit Line Clock (TxSERCLK): The exact function of this pin depends on the mode of opera- tion selected, as described below. In Base-Rate Mode (1.544MHz/2.048MHz) - TxSERCLK: This clock signal is used by the transmit serial interface to latch the contents on the TxSER pin into the T1/E1 framer on the rising edge of TxSERCLK. This pin can be configured as input or output as described below. When TxSERCLK is configured as Input: This pin will be an input if the TxSERCLK is chosen as the timing source for the transmit framer. Users must provide a 1.544MHz clock rate to this input pin for T1 mode of opera- tion, and 2.048MHz clock rate in E1 mode. When TxSERCLK is configured as Output: This pin will be an output if either the recovered line clock or the MCLK PLL is chosen as the timing source for the T1/E1 transmit framer. The transmit framer will output a 1.544MHz clock rate in T1 mode of operation, and a 2.048MHz clock rate in E1 mode. DS1/E1 High-Speed Backplane Modes* - TxSERCLK as INPUT ONLY In this mode, TxSERCLK is an optional clock signal input which is used as the timing source for the transmit line inter- face, and is only required if TxSERCLK is chosen as the tim- ing source for the transmit framer. If TxSERCLK is chosen as the timing source, system equipment should provide 1.544MHz (For T1 mode) or 2.048MHz (For E1 mode) to the TxSERCLK pin. TxSERCLK is not required if either the recov- ered clock or MCLK PLL is chosen as the timing source of the device. High speed or multiplexed data is latched into the device using the TxMSYNC/TxINCLK high-speed clock signal. DS1 or E1 Framer Bypass Mode - TxLINECLK In this mode, TxSERCLK is used as the transmit line clock (TxLINECLK) to the LIU. NOTE: *High-speed backplane modes include (For T1/E1) 2.048MVIP, 4.096MHz, 8.192MHz, 16.384MHz HMVIP, H.100, Bit-multiplexed modes, and (For T1 only) 12.352MHz Bit-multiplexed mode. NOTE: In DS1 high-speed modes, the DS-0 data is mapped into an E1 frame by ignoring every fourth time slot (don’t care). NOTE: This pin is internally pulled “High”. TRANSMIT SYSTEM SIDE INTERFACE SIGNAL NAME 128-PIN# 80-PIN# TYPE OUTPUT DRIVE(MA) DESCRIPTION |
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