Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

XRT91L34 Datasheet(PDF) 4 Page - Exar Corporation

Part # XRT91L34
Description  QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
Download  38 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  EXAR [Exar Corporation]
Direct Link  http://www.exar.com
Logo EXAR - Exar Corporation

XRT91L34 Datasheet(HTML) 4 Page - Exar Corporation

  XRT91L34 Datasheet HTML 1Page - Exar Corporation XRT91L34 Datasheet HTML 2Page - Exar Corporation XRT91L34 Datasheet HTML 3Page - Exar Corporation XRT91L34 Datasheet HTML 4Page - Exar Corporation XRT91L34 Datasheet HTML 5Page - Exar Corporation XRT91L34 Datasheet HTML 6Page - Exar Corporation XRT91L34 Datasheet HTML 7Page - Exar Corporation XRT91L34 Datasheet HTML 8Page - Exar Corporation XRT91L34 Datasheet HTML 9Page - Exar Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 4 / 38 page
background image
XRT91L34
IV
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
REV. 1.0.1
TABLE OF CONTENTS
GENERAL DESCRIPTION .................................................................................................1
FIGURE 1. BLOCK DIAGRAM OF XRT91L34 ...................................................................................................................................... 1
APPLICATIONS ...........................................................................................................................................2
FEATURES
......................................................................................................................................................2
FIGURE 2. 128 LQFP PIN OUT OF THE XRT91L34 (TOP VIEW)........................................................................................................ 3
ORDERING INFORMATION .....................................................................................................................3
TABLE OF CONTENTS .......................................................................................................... IV
PIN DESCRIPTIONS ..........................................................................................................6
HARDWARE CONTROL ....................................................................................................................................6
RECEIVER SECTION........................................................................................................................................9
POWER AND GROUND ..................................................................................................................................10
SERIAL
MICROPROCESSOR INTERFACE ......................................................................................................11
1.0 FUNCTIONAL DESCRIPTION .............................................................................................................12
1.1 HARDWARE MODE VS. HOST MODE .......................................................................................................... 12
1.2 STS-12/STM-4 AND STS-3/STM-1 AND STS-1/STM-0 MODE OF OPERATION ......................................... 12
TABLE 1: CHANNEL DATA RATE SELECTION .................................................................................................................................... 12
1.3 REFERENCE CLOCK INPUT ......................................................................................................................... 13
TABLE 2: CDR REFERENCE FREQUENCY OPTIONS (LVDS/ DIFF LVPECL OR SINGLE-ENDED LVTTL/LVCMOS)............................ 13
FIGURE 3. REFERENCE CLOCK DESIGN OPTIONS............................................................................................................................ 13
2.0 RECEIVE SECTION .............................................................................................................................14
2.1 RECEIVE SERIAL INPUT ............................................................................................................................... 14
FIGURE 4. RECEIVE SERIAL INPUT INTERFACE USING LVDS/DIFF LVPECL DC COUPLING INTERNAL TERM....................................... 14
FIGURE 5. RECEIVE SERIAL INPUT INTERFACE USING DIFF LVPECL AC COUPLING INTERNAL TERMINATION ..................................... 15
2.2 RECEIVE CLOCK AND DATA RECOVERY .................................................................................................. 15
TABLE 3: CLOCK AND DATA RECOVERY UNIT PERFORMANCE .......................................................................................................... 16
2.2.1 INTERNAL CLOCK AND DATA RECOVERY DISABLE ........................................................................................... 16
2.3 EXTERNAL RECEIVE LOOP FILTER CAPACITORS ................................................................................... 16
FIGURE 6. EXTERNAL LOOP FILTERS .............................................................................................................................................. 16
2.4 INTERNAL DIGITAL LOSS OF SIGNAL AND EXTERNAL SIGNAL DETECTION ...................................... 17
FIGURE 7. LOSS OF SIGNAL DECLARATION CIRCUIT ........................................................................................................................ 17
TABLE 4: EXTERNAL LOS DECLARATION POLARITY SETTING........................................................................................................... 17
2.5 MULTICHANNEL RECOVERED OUTPUT INTERFACE ............................................................................... 18
FIGURE 8. MULTICHANNEL RECOVERED OUTPUT INTERFACE BLOCK................................................................................................ 18
2.6 DIFFERENTIAL RECOVERED DATA OUTPUT TIMING ............................................................................... 19
FIGURE 9. DIFFERENTIAL RECOVERED OUTPUT TIMING ................................................................................................................... 19
TABLE 5: RECOVERED DATA OUTPUT TIMING (STS-12/STM-4 OPERATION).................................................................................... 19
TABLE 6: RECOVERED DATA OUTPUT TIMING (STS-3/STM-1 OPERATION)...................................................................................... 19
TABLE 7: RECOVERED DATA OUTPUT TIMING (STS-1/STM-0 OPERATION)...................................................................................... 19
3.0 JITTER PERFORMANCE ....................................................................................................................20
3.1 SONET JITTER REQUIREMENTS ................................................................................................................. 20
3.1.1 RX JITTER TOLERANCE: .......................................................................................................................................... 20
FIGURE 10. GR-253/G.783 JITTER TOLERANCE MASK ................................................................................................................... 20
FIGURE 11. XRT91L34 MEASURED JITTER TOLERANCE AT 51.84 MBPS STS-1/STM-0 .................................................................. 20
FIGURE 12. XRT91L34 MEASURED JITTER TOLERANCE AT 155.52 MBPS STS-3/STM-1 ................................................................ 21
FIGURE 13. XRT91L34 MEASURED JITTER TOLERANCE AT 622.08 MBPS STS-12/STM-4 .............................................................. 21
3.1.2 RX JITTER TRANSFER .............................................................................................................................................. 22
FIGURE 14. XRT91L34 MEASURED JITTER TRANSFER AT 51.84 MBPS STS-1/STM-0 .................................................................... 22
FIGURE 15. XRT91L34 MEASURED JITTER TRANSFER AT 155.52 MBPS STS-3/STM-1 .................................................................. 22
FIGURE 16. XRT91L34 MEASURED JITTER TRANSFER AT 622.08 MBPS STS-12/STM-4 ................................................................ 23
4.0 SERIAL MICROPROCESSOR INTERFACE BLOCK ..........................................................................24
FIGURE 17. SIMPLIFIED BLOCK DIAGRAM OF THE SERIAL MICROPROCESSOR INTERFACE ................................................................. 24
4.1 SERIAL TIMING INFORMATION .................................................................................................................... 24
FIGURE 18. TIMING DIAGRAM FOR THE SERIAL MICROPROCESSOR INTERFACE ................................................................................ 24
4.2 16-BIT SERIAL DATA INPUT DESCRITPTION ............................................................................................. 25
4.2.1 R/W (SCLK1) ............................................................................................................................................................... 25
4.2.2 A[5:0] (SCLK2 - SCLK7)............................................................................................................................................. 25
4.2.3 X (DUMMY BIT SCLK8) .............................................................................................................................................. 25
4.2.4 D[7:0] (SCLK9 - SCLK16)........................................................................................................................................... 25
4.3 8-BIT SERIAL DATA OUTPUT DESCRIPTION ............................................................................................. 25


Similar Part No. - XRT91L34

ManufacturerPart #DatasheetDescription
logo
Exar Corporation
XRT91L34IVF EXAR-XRT91L34IVF Datasheet
166Kb / 2P
   China RoHS Fully Compliant
More results

Similar Description - XRT91L34

ManufacturerPart #DatasheetDescription
logo
Exar Corporation
XRT91L31 EXAR-XRT91L31 Datasheet
339Kb / 41P
   STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
XRT91L30 EXAR-XRT91L30 Datasheet
367Kb / 40P
   STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
XRT91L31IQ-F EXAR-XRT91L31IQ-F Datasheet
832Kb / 41P
   STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
XRT91L30_0611 EXAR-XRT91L30_0611 Datasheet
694Kb / 39P
   STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
XRT91L31 EXAR-XRT91L31_08 Datasheet
832Kb / 41P
   STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
XRT91L32 EXAR-XRT91L32 Datasheet
650Kb / 37P
   STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
logo
List of Unclassifed Man...
SI5013 ETC1-SI5013 Datasheet
153Kb / 24P
   OC-12/3, STM-4/1 SONET/SDH CDR IC WITH LIMITING AMPLIFIER
logo
Silicon Laboratories
SI5013-D-GM SILABS-SI5013-D-GM Datasheet
215Kb / 26P
   OC-12/3, STM-4/1 SONET/SDH CDR IC WITH LIMITING AMPLIFIER
SI5013 SILABS-SI5013 Datasheet
400Kb / 26P
   OC-12/3, STM-4/1 SONET/SDH CDR IC WITH LIMITING AMPLIFIER
logo
Exar Corporation
XRT94L43 EXAR-XRT94L43 Datasheet
180Kb / 7P
   SONET/SDH STS-12/STM-4 TO E3/DS3/STS-1 MAPPER/DEMAPPER
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.NET
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com