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XRT91L31 Datasheet(PDF) 4 Page - Exar Corporation |
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XRT91L31 Datasheet(HTML) 4 Page - Exar Corporation |
4 / 41 page XRT91L31 4 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER REV. 1.0.2 GENERAL DESCRIPTION .................................................................................................1 APPLICATIONS ...........................................................................................................................................1 FIGURE 1. BLOCK DIAGRAM OF XRT91L31 ...................................................................................................................................... 1 FEATURES ......................................................................................................................................................2 FIGURE 2. 64 QFP PIN OUT OF THE XRT91L31 (TOP VIEW)............................................................................................................ 3 TABLE 1: ORDERING INFORMATION ................................................................................................................................................... 3 PIN DESCRIPTIONS ..........................................................................................................6 .....................................................................................................................................................................6 TABLE 2: HARDWARE CONTROL ....................................................................................................................................................... 6 TRANSMITTER SECTION ..................................................................................................................................9 RECEIVER SECTION......................................................................................................................................11 POWER AND GROUND ..................................................................................................................................12 1.0 FUNCTIONAL DESCRIPTION .............................................................................................................14 1.1 STS-12/STM-4 AND STS-3/STM-1 MODE OF OPERATION ......................................................................... 14 1.2 CLOCK INPUT REFERENCE FOR CLOCK MULTIPLIER (SYNTHESIZER) UNIT ...................................... 14 TABLE 3: CMU REFERENCE FREQUENCY OPTIONS (DIFFERENTIAL OR SINGLE-ENDED) ................................................................... 14 1.3 DATA LATENCY ............................................................................................................................................. 14 TABLE 4: DATA INGRESS TO DATA EGRESS LATENCY ....................................................................................................................... 14 2.0 RECEIVE SECTION .............................................................................................................................15 2.1 RECEIVE SERIAL INPUT ............................................................................................................................... 15 FIGURE 3. RECEIVE SERIAL INPUT INTERFACE BLOCK ..................................................................................................................... 15 2.2 RECIEVE SERIAL DATA INPUT TIMING ...................................................................................................... 16 FIGURE 4. RECEIVE HIGH-SPEED SERIAL DATA INPUT TIMING DIAGRAM .......................................................................................... 16 TABLE 5: RECEIVE HIGH-SPEED SERIAL DATA INPUT TIMING (STS-12/STM-4 OPERATION) ............................................................. 16 TABLE 6: RECEIVE HIGH-SPEED SERIAL DATA INPUT TIMING (STS-3/STM-1 OPERATION) ............................................................... 16 ...................................................................................................................................................................16 2.3 RECEIVE CLOCK AND DATA RECOVERY .................................................................................................. 17 TABLE 7: CLOCK DATA RECOVERY UNIT REFERENCE CLOCK SETTINGS ............................................................................................ 17 TABLE 8: CDR AUXREFCLK REFERENCE FREQUENCY REQUIREMENT FOR CLOCK AND DATA RECOVERY ..................................... 17 2.3.1 INTERNAL CLOCK AND DATA RECOVERY BYPASS ............................................................................................ 17 FIGURE 5. INTERNAL CLOCK AND DATA RECOVERY BYPASS............................................................................................................ 18 2.4 EXTERNAL RECEIVE LOOP FILTER CAPACITORS ................................................................................... 19 FIGURE 6. EXTERNAL LOOP FILTERS .............................................................................................................................................. 19 2.5 LOSS OF SIGNAL .......................................................................................................................................... 19 FIGURE 7. LOS DECLARATION CIRCUIT .......................................................................................................................................... 19 2.6 SONET FRAME BOUNDARY DETECTION AND BYTE ALIGNMENT RECOVERY .................................... 20 2.7 RECEIVE SERIAL INPUT TO PARALLEL OUTPUT (SIPO) ......................................................................... 20 FIGURE 8. SIMPLIFIED BLOCK DIAGRAM OF SIPO ...........................................................................................................................20 2.8 RECEIVE PARALLEL OUTPUT INTERFACE ............................................................................................... 21 FIGURE 9. RECEIVE PARALLEL OUTPUT INTERFACE BLOCK ............................................................................................................. 21 2.9 DISABLE PARALLEL RECEIVE DATA OUTPUT UPON LOS ..................................................................... 21 2.10 RECEIVE PARALLEL DATA OUTPUT TIMING .......................................................................................... 22 FIGURE 10. RECEIVE PARALLEL OUTPUT TIMING ............................................................................................................................ 22 TABLE 9: RECEIVE PARALLEL DATA OUTPUT TIMING (STS-12/STM-4 OPERATION) ......................................................................... 22 TABLE 10: RECEIVE PARALLEL DATA OUTPUT TIMING (STS-3/STM-1 OPERATION) ......................................................................... 22 TABLE 11: PECL AND TTL RECEIVE OUTPUTS TIMING SPECIFICATION ............................................................................................ 23 3.0 TRANSMIT SECTION ..........................................................................................................................24 3.1 TRANSMIT PARALLEL INPUT INTERFACE ................................................................................................. 24 FIGURE 11. TRANSMIT PARALLEL INPUT INTERFACE BLOCK............................................................................................................. 24 3.2 TRANSMIT PARALLEL DATA INPUT TIMING .............................................................................................. 25 FIGURE 12. TRANSMIT PARALLEL INPUT TIMING .............................................................................................................................. 25 TABLE 12: TRANSMIT PARALLEL DATA INPUT TIMING (STS-12/STM-4 OPERATION)......................................................................... 25 ...................................................................................................................................................................25 TABLE 13: TRANSMIT PARALLEL DATA INPUT TIMING (STS-3/STM-1 OPERATION)........................................................................... 25 ...................................................................................................................................................................25 3.3 ALTERNATE TRANSMIT PARALLEL BUS CLOCK INPUT OPTION .......................................................... 26 FIGURE 13. ALTERNATE TRANSMIT PARALLEL INPUT INTERFACE BLOCK (PARALLEL CLOCK INPUT OPTION) ...................................... 26 3.4 ALTERNATE TRANSMIT PARALLEL DATA INPUT TIMING ....................................................................... 26 FIGURE 14. ALTERNATE TRANSMIT PARALLEL INPUT TIMING............................................................................................................ 26 TABLE 14: ALTERNATE TRANSMIT PARALLEL DATA INPUT TIMING (STS-12/STM-4 OPERATION) ...................................................... 27 ...................................................................................................................................................................27 |
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