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XRT91L34IV-F Datasheet(PDF) 8 Page - Exar Corporation

Part # XRT91L34IV-F
Description  QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
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Manufacturer  EXAR [Exar Corporation]
Direct Link  http://www.exar.com
Logo EXAR - Exar Corporation

XRT91L34IV-F Datasheet(HTML) 8 Page - Exar Corporation

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XRT91L34
8
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
REV. 1.0.1
DLOSDIS
/SDI
LVTTL,
LVCMOS
I
39
DLOS (Digital Loss of Signal) Disable
Hardware Mode Disables internal DLOS monitoring and auto-
matic muting of RXDO[3:0]P/N recovered data output pins upon
DLOS detection. DLOS is declared when the incoming data
stream has no transition for more than 2.5
µs. DLOS is cleared
when transitions are detected within a 128
µs interval sliding
window.
"Low" = Monitor & Mute recovered data upon DLOS declaration
"High" = Disable internal DLOS monitoring
This pin is provided with an internal pull-down.
Host Mode This pin is functions as the microprocessor Serial
Data Input.
POL0
POL1
POL2
POL3
LVTTL,
LVCMOS
I
126
124
36
34
Polarity for SDEXT Input
Controls the Signal Detect polarity convention of SDEXT.
"Low" = SDEXT is active "Low."
"High" = SDEXT is active "High."
NOTE: These pins have no function in Host Mode.
These pins are provided with internal pull-down.
SDEXT0
SDEXT1
SDEXT2
SDEXT3
LVTTL,
LVCMOS,
I
127
125
35
33
Signal Detect Input from Optical Module
When inactive, it will immediately declare a Loss of Signal
(LOS) condition and assert LOS register bit and mute the activ-
ity of the RXDO[3:0]P/N serial data output on the respective
channel.
"Active" = Normal Operation
"Inactive" = LOS Condition (SDEXT detects signal absence)
These pins are provided with internal pull-down.
REFCLKP
REFCLKN
LVDS,
Diff LVPECL
I
117
118
Reference Clock Input (77.76 MHz or 19.44 MHz)
This differential reference clock input will accept either a 77.76
MHz or a 19.44 MHz LVDS/Differential LVPECL clock source.
Pin CDRREFSEL determines the value used as the reference.
See Pin CDRREFSEL for more details. REFCLKP/N inputs are
internally biased to 1.2V via 15k
Ω resistance. These pins are
equipped with a 100
Ω line-to-line internal termination.
NOTE: In the event that TTLREFCLK LVTTL/LVCMOS input is
used instead of these differential inputs for clock
reference, the REFCLKP should be left unconnected
and REFCLKN should be tied to GND.
TTLREFCLK
LVTTL,
LVCMOS
I
120
TTL Reference Clock Input (77.76 MHz or 19.44 MHz)
This optional single-ended clock input reference can be used
instead of the differential REFCLKP/N input. It will accept
either a 77.76 MHz or a 19.44 MHz LVTTL clock source. Pin
CDRREFSEL determines the value used as the reference. See
Pin CDRREFSEL for more details.
NOTE:
In the event that REFCLKP/N differential inputs are
used instead of this LVTTL/LVCMOS input for clock
reference, the TTLREFCLK should be tied to ground.
This pin is provided with an internal pull-down.
NAME
LEVEL
TYPE
PIN
DESCRIPTION


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