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XR16L784IV Datasheet(PDF) 10 Page - Exar Corporation |
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XR16L784IV Datasheet(HTML) 10 Page - Exar Corporation |
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10 / 51 page  XR16L784 10 HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART REV. 1.2.3 2.7.3 Transmitter Operation in FIFO Mode The host may fill the transmit FIFO with up to 64 bytes of transmit data. The THR empty flag (LSR bit-5) is set whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the amount of data in the FIFO falls below its programmed trigger level. The transmit empty interrupt is enabled by IER bit-1. The TSR flag (LSR bit-6) is set when TSR/FIFO becomes empty. 2.8 Receiver The receiver section contains an 8-bit Receive Shift Register (RSR) and 64 bytes of FIFO which includes a byte-wide Receive Holding Register (RHR). The RSR uses the 16X for timing. It verifies and validates every bit on the incoming character in the middle of each data bit. On the falling edge of a start or false start bit, an internal receiver counter starts counting at the 16X. After 8 clocks the start bit period should be at the center of the start bit. At this time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver from assembling a false character. The rest of the data bits and stop bits are sampled and validated in this same manner to prevent false framing. If there were any error(s), they are reported in the LSR register bits 2-4. Upon unloading the receive data byte from RHR, the receive FIFO pointer is bumped and the error tags are immediately updated to reflect the status of the data byte in RHR register. RHR can generate a receive data ready interrupt upon receiving a character or delay until it reaches the FIFO trigger level. Furthermore, data delivery to the host is guaranteed by a receive data ready time-out interrupt when data is not received for 4 word lengths as defined by LCR[1:0] plus 12 bits time. This is equivalent to 3.7- 4.6 character times. The RHR interrupt is enabled by IER bit-0. FIGURE 6. TRANSMITTER OPERATION IN NON-FIFO MODE FIGURE 7. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE Transmit Holding Register (THR) Transmit Shift Register (TSR) Data Byte L S B M S B THR Interrupt (ISR bit-1) Enabled by IER bit-1 TXNOFIFO1 16X or 8X Clock Transm it Data Shift Register (TSR) Transm it Data Byte THR Interrupt (ISR bit-1) falls below the program m ed Trigger Level and then when becom es em pty. FIFO is Enabled by FCR bit-0=1 Transm it FIFO 16X or 8X Clock Auto CTS Flow Control (CTS# pin) Auto Software Flow Control Flow Control Characters (Xoff1/2 and Xon1/2 Reg. TXF IF O 1 |
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