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XR16L784 Datasheet(PDF) 11 Page - Exar Corporation |
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XR16L784 Datasheet(HTML) 11 Page - Exar Corporation |
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11 / 51 page  XR16L784 11 REV. 1.2.3 HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART 2.8.1 Receive Holding Register (RHR) - Read-Only The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift Register. It provides the receive data interface to the host processor. The RHR register is part of the receive FIFO of 64 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data byte are immediately updated in the LSR bits 2-4. NOTE: Table-B selected as Trigger Table for Figure 9 (Table 14). FIGURE 8. RECEIVER OPERATION IN NON-FIFO MODE FIGURE 9. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE Receive Data Shift Register (RSR) Receive Data Byte and Errors RHR Interrupt (ISR bit-2) Receive Data Holding Register (RHR) RXFIFO1 16X or 8X Clock Receive Data Characters Data Bit Validation Error Tags in LSR bits 4:2 Receive Data Shift Register (RSR) RXFIFO1 16X or 8X Clock 64 bytes by 11-bit wide FIFO Receive Data Characters FIFO Trigger=16 Example: - RX FIFO trigger level selected at 16 bytes (See Note Below) Data fills to 24 Data falls to 8 Data Bit Validation Receive Data FIFO Receive Data Receive Data Byte and Errors RHR Interrupt (ISR bit-2) programmed for desired FIFO trigger level. FIFO is Enabled by FCR bit-0=1 RTS# de-asserts when data fills above the flow control trigger level to suspend remote transmitter. Enable by EFR bit-6=1, MCR bit-2. RTS# re-asserts when data falls below the flow control trigger level to restart remote transmitter. Enable by EFR bit-6=1, MCR bit-2. |
Similar Part No. - XR16L784 |
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Similar Description - XR16L784 |
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