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XR16M2752IJ44 Datasheet(PDF) 8 Page - Exar Corporation |
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XR16M2752IJ44 Datasheet(HTML) 8 Page - Exar Corporation |
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8 / 51 page  XR16M2752 8 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO REV. 1.0.0 2.5 Channel A and B Internal Registers Each UART channel in the M2752 has a set of enhanced registers for control, monitoring and data loading and unloading. The configuration register set is compatible to those already available in the standard single 16C550 and dual ST16C2550. These registers function as data holding registers (THR/RHR), interrupt status and control registers (ISR/IER), a FIFO control register (FCR), receive line status and control registers (LSR/ LCR), modem status and control registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/ DLM/DLD), and a user accessible Scratchpad Register (SPR). Beyond the general 16C2550 features and capabilities, the M2752 offers enhanced feature registers (EMSR, FLVL, EFR, Xon/Xoff 1, Xon/Xoff 2, FCTR, TRG, FC) that provide automatic RTS and CTS hardware flow control, Xon/Xoff software flow control, automatic RS-485 half-duplex direction output enable/disable, FIFO trigger level control, and FIFO level counters. All the register functions are discussed in full detail later in “Section 3.0, UART Internal Registers” on page 21. 2.6 DMA Mode The device does not support direct memory access. The DMA Mode (a legacy term) in this document doesn’t mean “direct memory access” but refers to data block transfer operation. The DMA mode affects the state of the RXRDY# A/B and TXRDY# A/B output pins. The transmit and receive FIFO trigger levels provide additional flexibility to the user for block mode operation. The LSR bits 5-6 provide an indication when the transmitter is empty or has an empty location(s) for more data. The user can optionally operate the transmit and receive FIFO in the DMA mode (FCR bit-3=1). When the transmit and receive FIFO are enabled and the DMA mode is disabled (FCR bit-3 = 0), the M2752 is placed in single-character mode for data transmit or receive operation. When DMA mode is enabled (FCR bit-3 = 1), the user takes advantage of block mode operation by loading or unloading the FIFO in a block sequence determined by the programmed trigger level. In this mode, the M2752 sets the TXRDY# pin when the transmit FIFO becomes full, and sets the RXRDY# pin when the receive FIFO becomes empty. The following table shows their behavior. Also see Figures 17 through 22. TABLE 1: CHANNEL A AND B SELECT CS# CHSEL FUNCTION 1 X UART de-selected 0 1 Channel A selected 0 0 Channel B selected TABLE 2: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE PINS FCR BIT-0=0 (FIFO DISABLED) FCR BIT-0=1 (FIFO ENABLED) FCR Bit-3 = 0 (DMA Mode Disabled) FCR Bit-3 = 1 (DMA Mode Enabled) RXRDY# A/B LOW = 1 byte. HIGH = no data. LOW = at least 1 byte in FIFO. HIGH = FIFO empty. HIGH to LOW transition when FIFO reaches the trigger level, or time-out occurs. LOW to HIGH transition when FIFO empties. TXRDY# A/B LOW = THR empty. HIGH = byte in THR. LOW = FIFO empty. HIGH = at least 1 byte in FIFO. LOW = FIFO has at least 1 empty location. HIGH = FIFO is full. |
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