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XR16V564 Datasheet(PDF) 5 Page - Exar Corporation |
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XR16V564 Datasheet(HTML) 5 Page - Exar Corporation |
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5 / 55 page  XR16V564/564D 5 REV. 1.0.2 2.25V TO 3.6V QUAD UART WITH 32-BYTE FIFO CSB# (A3) 9 11 20 33 I When 16/68# pin is HIGH, this input is chip select B (active low) to enable channel B in the device. When 16/68# pin is LOW, this input becomes address line A3 which is used for channel selection in the Motorola bus interface. CSC# (A4) 27 38 50 73 I When 16/68# pin is HIGH, this input is chip select C (active low) to enable channel C in the device. When 16/68# pin is LOW, this input becomes address line A4 which is used for channel selection in the Motorola bus interface. CSD# (VCC) 31 42 54 68 I When 16/68# pin is HIGH, this input is chip select D (active low) to enable channel D in the device. When 16/68# pin is LOW, this input is not used and should be connected VCC. INTA (IRQ#) 4 6 15 27 O (OD) When 16/68# pin is HIGH for Intel bus interface, this ouput becomes channel A interrupt output. The output state is defined by the user and through the software setting of MCR[3]. INTA is set to the active mode when MCR[3] is set to a logic 1. INTA is set to the three state mode when MCR[3] is set to a logic 0 (default). See MCR[3]. When 16/68# pin is LOW for Motorola bus interface, this output becomes device interrupt output (active low, open drain). An external pull-up resistor is required for proper operation. INTB INTC INTD (N.C.) 10 26 32 12 37 43 21 49 55 34 67 74 O When 16/68# pin is HIGH for Intel bus interface, these ouputs become the interrupt outputs for channels B, C, and D. The output state is defined by the user through the software setting of MCR[3]. The interrupt outputs are set to the active mode when MCR[3] is set to a logic 1 and are set to the three state mode when MCR[3] is set to a logic 0 (default). See MCR[3]. When 16/68# pin is LOW for Motorola bus interface, these outputs are unused and will stay at logic zero level. Leave these outputs unconnected. TXRDY# - - 39 55 O Transmitter Ready (active low). This output is a logi- cally ANDed status of TXRDY# A-D. See Table 5. If this output is unused, leave it unconnected. RXRDY# - - 38 54 O Receiver Ready (active low). This output is a logically ANDed status of RXRDY# A-D. See Table 5. If this output is unused, leave it unconnected. Pin Description NAME 48-QFN PIN # 64-LQFP PIN # 68-PLCC PIN # 80-LQFP PIN # TYPE DESCRIPTION |
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