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FDMF6704V Rev. C

Power Loss and Efficiency

Measurement and Calculation

Refer to Figure 20 for power loss testing method. Power loss

calculation are as follows:

(W)

(W)

(W)

(W)

(%)

(%)

PCB Layout Guideline

Figure 21 shows a proper layout example of FDMF6704V and

critical parts. All of high current flow path, such as VIN, VSWH,

stable current flow, heat radiation and system performance.

Following is a guideline which the PCB designer should

consider:

1. Input ceramic bypass capacitors must be close to VIN and

PGND pin of FDMF6704V to help reduce the input current ripple

component induced by switching operation.

2. The VSWH copper trace serves two purposes. In addition to

being the high frequency current path from the DrMOS package

to the output inductor, it also serves as heatsink for the lower

FET in the DrMOS package. The trace should be short and wide

enough to present a low impedance path for the high frequency,

high current flow between the DrMOS and inductor in order to

minimize losses and temperature rise. Please note that the

VSWH node is a high voltage and high frequency switching

node with high noise potential. Care should be taken to

minimize coupling to adjacent traces. Additionally, since this

copper trace also acts as heatsink for the lower FET, tradeoff

must be made to use the largest area possible to improve

DrMOS cooling while maintaining acceptable noise emission.

3. Output inductor location should be as close as possible to the

FDMF6704V to minimize lower power loss due to copper trace.

Care should be taken so that inductor dissipation does not heat

the DrMOS.

very effective at minimizing ringing. In most cases, no snubber

will be required. If a snubber is used, it should be placed near

the FDMF6704V. The resistor and capacitor need to be of

proper size for the power dissipation.

5. Place ceramic bypass capacitor and BOOT capacitor as

close as possible to the VCIN and BOOT pins of the

FDMF6704V to ensure clean and stable power. Routing width

and length should be considered as well.

6. Include a trace from PHASE to VSWH in order to improve

noise margin. Keep the trace as short as possible.

7. The layout should include the option to insert a small value

series boot resistor between boot cap and BOOT pin. The boot

possible. The boot resistor is normally not required, but is

effective at improving noise operating margin in multi phase

designs that may have noise issues due to ground bounce and

high negative VSWH ringing. The VIN and PGND pins handle

large current transients with frequency components above

100 MHz. If possible, these package pins should be connected

directly to the VIN and board GND planes. The use of thermal

relief traces in series with these pins is discouraged since this

will add inductance to the power path. This added inductance in

series with the PGND pin will degrade system noise immunity

by increasing negative VSWH ringing.

8. CGND pad and PGND pins should be connected by plane

GND copper with multiple vias for stable grounding. Poor

grounding can create a noise transient offset voltage level

between CGND and PGND. This could lead to fault operation of

gate driver and MOSFET.

9. Ringing at the BOOT pin is most effectively controlled by

close placement of the boot capacitor. Do not add an additional

BOOT to PGND capacitor. This may lead to excess current flow

through the BOOT diode.

10. SMOD#, DISB# and PWM pins don’t have internal pull up or

pull down resistors. They should not be left floating. These pins

should not have any noise filter caps.

11. Use multiple vias on each copper area to interconnect top,

inner and bottom layers to help smooth current flow and heat

conduction. Vias should be relatively large and of reasonable

close to the DrMOS module and on the same side of the PCB

as the module. If not feasible, they should be connected from

the backside via a network of low inductance vias.

Figure 20. Power Loss Measurement Block Diagram

DISB#

PWM

CGND PGND

VCIN

VIN

BOOT

VSWH

DISB#

PWM Input

VDRV

SMOD#

PHASE

A

A

V

SMOD#

A