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SG1577A Datasheet(PDF) 11 Page - Fairchild Semiconductor |
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SG1577A Datasheet(HTML) 11 Page - Fairchild Semiconductor |
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11 / 15 page  © 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com SG1577A • Rev. 1.0.0 11 Functional Description The SG1577A is a dual-channel voltage-mode PWM controller. It has two sets of synchronous MOSFET driving circuits. The two channels are running 180- degrees out of phase. The following descriptions highlight the advantages of the SG1577A design. Soft Start An internal start-up current (35/15µA) flows out of SS/EN pin to charge an external capacitor. During the startup sequence, SG1577A isn’t enabled until the SS/ENB pin is higher than 1.2V. From 1.2V to (1.2 + 1.6 x DON / DON_MAX) V, the PWM duty cycle gradually increases following the SS/ENB pin voltage to bring output rising. After (1.2 + 1.6 x DON / DON_MAX) V, the soft-start period ends and SS/ENB pin continually rises to 4.8V. When input power is abnormal, the external capacitor on the SS pin is shorted to ground and the chip is disabled. Over-Current Protection (OCP) Over-current protection is implemented by sensing the voltage drop across the drain and the source of external high-side MOSFET. Over-current protection is triggered when the voltage drop on external high-side MOSFET’s RDS(ON) is greater than the programmable current limit voltage threshold. 120µA flowing through an external resistor between input voltage and the CLP pin sets the threshold of current limit voltage. When over-current condition is true, the system is protected against the cycle-by-cycle current limit. A counter counts a series of over-current peak values to eight cycles; the soft-start capacitor is discharged by a 50µA current until the voltage on SS pin reaches 1.2V. During the discharge period, the high-side driver is turned off and the low- side driver is turned on. Once the voltage on SS/ENB pin is under 1.2V, the normal soft-start sequence is initiated and the 35/15µA current charges the soft-start capacitor again. IL(OCP)= [(RSENSE x IOCSET + VOFFSET) / RDS(ON) - (VIN - VOUT) x VOUT / (fOSC x LOUT x VIN x 2) ] (2) where VOFFSET ( ≒ 10mV) is the offset voltage contributed by the internal OCP comparator. Error Amplifier The IN1 and IN2 pins are connected to the corresponding internal error amplifier’s inverting input and the outputs of the error amplifiers are connected to the corresponding COMP1 and COMP2 pins. The COMP1 and COMP2 pins are available for control-loop compensation externally. Non-inverting inputs are internally tied to a fixed 0.7V ± 1.5% reference voltage. Oscillator Operation The SG1577A has a frequency-programmable oscillator. The oscillator is running at 61kHz when the RT pin is floating. The oscillator frequency can be adjusted from 61kHz up to 340kHz by an external resistor RRT between RT pin and the ground. The oscillator generates a sawtooth wave that has 90% rising duty. Sawtooth wave voltage threshold is from 1.2V to 2.8V. The frequency of oscillator can be programmed according to the following equation: fOSC, RT(kHz) = 61kHz + 8522 / RRT(kΩ) (3) Output Driver The high-side gate drivers need an external bootstrapping circuit to provide the required boost voltage. The highest gate driver’s output (15V is the allowed) on high-side and low-side MOSFETs forces external MOSFETs to have the lowest RDS(ON), which results in higher efficiency. Over-Temperature Protection (OTP) The device is over-temperature protected. When chip temperature is over 150 oC, the chip enters tri-state (high-side driver is turned off). The hysteresis is 20 oC. Type II Compensation Design (for Output Capacitors with High ESR) SG1577A is a voltage-mode controller; the control loop is a single voltage feedback path, including an error amplifier and PWM comparator, as shown in Figure 23. To achieve fast transient response and accurate output regulation, an adequate compensator design is necessary. A stable control loop has a 0dB gain crossing with -20dB/decade slope and a phase margin greater than 45°. Figure 23. Closed Loop SS1 2 1 2 SS1 1 SS1 t t t ; t 15µA 1.4V) - 0.9 12 5 1.6 (1.2V C ; t 35uA 1.2V) - (1.4V C = + × = × + × × = × SS2 2 1 2 SS2 1 SS2 t t t ; t 15µA 1.4V) - 0.9 12 3.3 1.6 (1.2V C ; t 35µA 1.2V) - (1.4V C = + × = × + × × = × shift - time 3 4 4 SS2 SS2 3 SS1 t t - t ; t 35µA 0.3V) - (1.2V C 15µA 0.3V C ; t 35µA 1.2V C = = × + × × = × (1) |
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