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XRS10L120IL Datasheet(PDF) 6 Page - Exar Corporation |
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XRS10L120IL Datasheet(HTML) 6 Page - Exar Corporation |
6 / 36 page EXSTOR XRS10L120 6 SERIAL ATA II: PORT MULTIPLIER REV. 1.06 3.0 FUNCTIONAL DESCRIPTION A top-level view of the XRS10L120 is shown in Figure 3 outlining the interfaces to the device and the required support components. The data path can be seen at the top of the device. This includes the output transmit and input receive paths at the top left, providing the upstream interface to the host, and the two output transmit and input receive paths at the top right, providing the downstream interface to the target devices. The clocking, control, and configuration interfaces are shown below the dotted line. The XRS10L120 incorporates identical instantiations of a dual-channel Serial ATA II 3 Gbps PHY macro. This common building block provides a uniform implementation with common characteristics and a common register map, but provides a functional implementation of independent PHY blocks. Digital logic implementations of Serial ATA link layer blocks along with port multiplier logic provide the remainder of the data path within the XRS10L120. In addition, management and control interfaces including an MDIO interface for FIGURE 3. XRS10L120 INTERFACES SIT_P/N SIR_P/N DRACT[1:0] RESETB PWRDNB MDC MDIO RBIAS SOT_P/N[1:0] SOR_P/N[1:0] CMU_REF_P/N XOD XOG TCK TDI TDO TMS TRST Serial ATA Upstream Interface to HBAs Control and Status Interface Configuration Interface Serial ATA Downstream Interface to Devices Reference Clock Crystal Oscillator I/O JTAG Interface VDDA Calibration Resistor 49.9 Ω ± 0.5% PS_SIDEBAND_B PORTSEL |
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