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XRS10L210IV-F Datasheet(PDF) 9 Page - Exar Corporation

Part # XRS10L210IV-F
Description  SERIAL ATA II: PORT SELECTOR
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Manufacturer  EXAR [Exar Corporation]
Direct Link  http://www.exar.com
Logo EXAR - Exar Corporation

XRS10L210IV-F Datasheet(HTML) 9 Page - Exar Corporation

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EXSTOR - 1 XRS10L210
9
REV. 1.04
SERIAL ATA II: PORT SELECTOR
3.0
FUNCTIONAL DESCRIPTION
A top-level view of the XRS10L210 is shown in Figure 4 outlining the interfaces to the device and the required
support components. The data path can be seen at the top of the device. This includes the two output transmit
and input receive paths at the top left, providing the upstream interface to the host, and the two output transmit
and input receive paths at the top right, providing the downstream interface to the target devices. The clocking,
control, and configuration interfaces are shown below the dotted line.
The XRS10L210 incorporates identical instantiations of a dual-channel Serial ATA II 3 Gbps PHY macro. This
common building block provides a uniform implementation with common characteristics and a common
register map, but provides a functional implementation of independent PHY blocks. Digital logic
implementations of Serial ATA link layer blocks along with port selector and port multiplier logic provide the
remainder of the data path within the XRS10L210. In addition, management and control interfaces including an
MDIO interface for register control, a JTAG interface for boundary scan purposes, and a resistor calibration
circuit complete the device. A block diagram of the XRS10L210 is shown in Figure 5.
FIGURE 4. XRS10L210 INTERFACES
FIGURE 5. XRS10L210 BLOCK DIAGRAM
SIT_P/N [1:0]
S IR _P/N[1:0]
D R AC T
H BAC T
R E SETB
PW R D N B
M D C
M D IO
R B IAS
SO T_P/N
SO R _P/N
C M U_R EF_P /N
X O D
X O G
TC K
TD I
TD O
TM S
TR ST
S erial A TA U pstream
Interface to H B A s
C ontrol and
S tatus
Interface
C onfiguration
Interface
S erial A TA D ow nstream
Interface to D evices
Reference C lock
Crystal O scillator I/O
JTA G
Interface
V D D A
C alibration R esistor
49.9
Ω ± 0.5%
PS_SID EBA N D _B
P O R TSEL
SATA II
3GPHY
SIT0
SIR0
PORT
SELECTOR
SATA II
3GPHY
SIT1
SIR1
SATA II
LINK
LAYER
RATE
ADJUST
FIFO
SATA II
LINK
LAYER
SATA II
3GPHY
SOR
SOT


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