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XRS10L220 Datasheet(PDF) 4 Page - Exar Corporation |
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XRS10L220 Datasheet(HTML) 4 Page - Exar Corporation |
4 / 38 page EXSTOR - 1 XRS10L220 4 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR REV. 1.02 2.0 PIN DESCRIPTIONS TABLE 1: XRS10L220 PIN DESCRIPTIONS PIN NAME PIN NUMBER I/O TYPE DESCRIPTION DATA INTERFACE SOTP0/SOTN0 68, 69 O CML AC Coupled Serial ATA Output Transmitters. These ports communicate from the XRS10L220 to downstream devices SOTP1/SOTN1 57, 56 SORP0/SORN0 65, 66 I Serial ATA Input Receivers. These ports receive signals from downstream devices SORP1/SORN1 60, 59 SITP0/SITN0 93, 94 O Serial ATA Output Transmitters. These ports communicate from the XRS10L220 to upstream hosts. SITP1/SITN1 82, 81 SIRP0/SIRN0 90, 91 I Serial ATA Input Receivers. These ports receive signals from upstream hosts. SIRP1/SIRN1 85, 84 CLOCK INTERFACE CMU_REFP/ CMU_REFN 46, 47 I CML AC Coupled Reference clock input XOD 43 0 Analog Crystal oscillator output XOG 44 I Analog Crystal oscillator input, 1.26V max MDIO INTERFACE SIGNALS MDC 3 I LVCMOS MDIO clock input, +3.3V LVCMOS MDIO 5 I/O LVCMOS MDIO data port, +3.3V LVCMOS. Open drain JTAG INTERFACE SIGNALS TCK 96 I LVCMOS JTAG test clock, +3.3V LVCMOS TDI 100 I JTAG test data in, +3.3V LVCMOS TDO 99 O JTAG test data out, +3.3V LVCMOS. Open drain If used to daisy chain JTAG devices, pull up externally using 3.3KOhm resistor. TMS 97 I JTAG mode select, +3.3V LVCMOS TRST 1 I JTAG test reset, +3.3V LVCMOS. Pull low externally using 3.3KOhm resistor for normal operation of the device. GENERAL CONTROL AND CONFIGURATION SIGNALS (CMOS) RBIAS 49 I Analog Connection point for calibration termination resistor. RESETB 75 I LVCMOS Active low reset pin, +3.3V LVCMOS. PWRDNB 52 I LVCMOS Active low power down signal for chip, +3.3V LVCMOS. DRACT[1:0] 73, 74 O LVCMOS Drive activity port for external LED. Active Low, 3.3V LVC- MOS, open drain |
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