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XRT83VL38 Datasheet(PDF) 6 Page - Exar Corporation

Part # XRT83VL38
Description  OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
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Manufacturer  EXAR [Exar Corporation]
Direct Link  http://www.exar.com
Logo EXAR - Exar Corporation

XRT83VL38 Datasheet(HTML) 6 Page - Exar Corporation

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XRT83VL38
II
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
Receive Equalizer Control and Transmit Line Build-Out Settings 30
Transmit and Receive Terminations 32
RECEIVER (Channels 0 - 7) 32
Internal Receive Termination Mode 32
Receive Termination Control 32
Simplified Diagram for the Internal Receive and Transmit Termination Mode 32
Receive Terminations 33
Simplified Diagram for T1 in the External Termination Mode (RXTSEL= 0 & TXTSEL= 0) 33
Simplified Diagram for E1 in External Receive Termination Mode (RXTSEL= 0) and Internal Trans-
mit Termination Mode (TXTEL= 1) 34
TRANSMITTER (Channels 0 - 7) 34
Transmit Termination Mode 34
Termination Select Control 34
External Transmit Termination Mode 34
Transmit Terminations 35
35
35
REDUNDANCY APPLICATIONS 35
TYPICAL REDUNDANCY SCHEMES 36
Simplified Block Diagram of the Transmit Section for 1:1 & 1+1 Redundancy 37
Simplified Block Diagram - Receive Section for 1:1 and 1+1 Redundancy 37
Simplified Block Diagram - Transmit Section for N+1 Redundancy 38
Simplified Block Diagram - Receive Section for N+1 Redundancy 39
Pattern Transmit and Detect Function 40
Pattern transmission control 40
Transmit All Ones (TAOS) 40
Network Loop Code Detection and Transmission 40
Loop-Code Detection Control 40
Transmit and Detect Quasi-Random Signal Source (TDQRSS) 41
Loop-Back Modes 42
Loop-back control in Hardware mode 42
Loop-back control in Host mode 42
Local Analog Loop-Back (ALOOP) 42
Local Analog Loop-back signal flow 42
Remote Loop-Back (RLOOP) 43
Remote Loop-back mode with jitter attenuator selected in receive path 43
Remote Loop-back mode with jitter attenuator selected in Transmit path 43
Digital Loop-Back (DLOOP) 44
Digital Loop-back mode with jitter attenuator selected in Transmit path 44
Dual Loop-Back 44
Signal flow in Dual loop-back mode 44
MICROPROCESSOR Parallel INTERFACE 45
Microprocessor interface signal description 45
Microprocessor Register Tables 46
Microprocessor Register Address 46
Microprocessor Register Bit Description 46
Microprocessor Register Descriptions 50


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