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XRT83VL38 Datasheet(PDF) 1 Page - Exar Corporation

Part # XRT83VL38
Description  OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
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Manufacturer  EXAR [Exar Corporation]
Direct Link  http://www.exar.com
Logo EXAR - Exar Corporation

XRT83VL38 Datasheet(HTML) 1 Page - Exar Corporation

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Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com
XRT83VL38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
JUNE 2009
REV. 1.0.0
GENERAL DESCRIPTION
The XRT83VL38 is a fully integrated Octal (eight
channel) long-haul and short-haul line interface unit
for T1 (1.544Mbps) 100
, E1 (2.048Mbps) 75 or
120
J1 110or BITS Timing applications.
In long-haul applications the XRT83VL38 accepts
signals that have been attenuated from 0 to 36dB at
772kHz in T1 mode (equivalent of 0 to 6000 feet of
cable loss) or 0 to 43dB at 1024kHz in E1 mode.
In T1 applications, the XRT83VL38 can generate five
transmit pulse shapes to meet the short-haul Digital
Cross-Connect (DSX-1) template requirements as
well as for Channel Service Units (CSU) Line Build
Out (LBO) filters of 0dB, -7.5dB -15dB and -22.5dB
as
required
by
FCC
rules.
It
also
provides
programmable transmit pulse generators for each
channel that can be used for output pulse shaping
allowing performance improvement over a wide
variety of conditions (The arbitrary pulse generators
are available in both T1 and E1 modes).
The XRT83VL38 provides both a parallel/serial Host
microprocessor interface as well as a Hardware
mode for programming and control.
Both the B8ZS and HDB3 encoding and decoding
functions are selectable as well as AMI. Two on-chip
crystal-less jitter attenuators with a 32 or 64 bit FIFO
can be placed in the receive and the transmit paths
with
loop
bandwidths
of
less
than
3Hz.
The
XRT83VL38 provides a variety of loop-back and
diagnostic features as well as transmit driver short
circuit detection and receive loss of signal monitoring.
It supports internal impedance matching for 75

100
 110 and 120 for both transmitter and
receiver. In the absence of the power supply, the
transmit outputs and receive inputs are tri-stated
allowing
for
redundancy
applications
The
chip
includes an integrated programmable clock multiplier
that can synthesize T1 or E1 master.
APPLICATIONS
BITS Timing
T1 Digital Cross-Connects (DSX-1)
ISDN Primary Rate Interface
CSU/DSU E1/T1/J1 Interface
T1/E1/J1 LAN/WAN Routers
Public switching Systems and PBX Interfaces
T1/E1/J1 Multiplexer and Channel Banks
Features (See Page 2)
FIGURE 1. BLOCK DIAGRAM OF THE XRT83VL38 T1/E1/J1 LIU (HOST MODE)
One of Eight channels, CHANNEL_n - (n= 0:7)
HW/HOST
WR_R/W
RD_DS
ALE_AS
CS
RDY_DTACK
INT
ICT
TPOS_n/TDATA_n
TNEG_n/CODES_n
TCLK_n
RCLK_n
RNEG_n/LCV_n
RPOS_n/RDATA_n
RLOS_n
RTIP_n
RRING_n
MASTER CLOCK SYNTHESIZER
QRSS
PATTERN
GENERATOR
DMO_n
TTIP_n
TRING_n
TXON_n
HDB3/
B8ZS
ENCODER
TX/RX JITTER
ATTENUATOR
TIMING
CONTROL
TX FILTER
& PULSE
SHAPER
LINE
DRIVER
DRIVE
MONITOR
LOCAL
ANALOG
LOOPBACK
REMOTE
LOOPBACK
DIGITAL
LOOPBACK
HDB3/
B8ZS
DECODER
TX/RX JITTER
ATTENUATOR
TIMING &
DATA
RECOVERY
PEAK
DETECTOR
& SLICER
QRSS
DETECTOR
NETWORK
LOOP
DETECTOR
RX
EQUALIZER
EQUALIZER
CONTROL
AIS
DETECTOR
LOS
DETECTOR
LBO[3:0]
LOOPBACK
ENABLE
NLCD ENABLE
QRSS ENABLE
PTS1
PTS2
D[7:0]
PCLK
A[7:0]
RESET
MICROPROCESSOR CONTROLLER
TEST
DFM
TAOS
ENABLE
MCLKE1
MCLKT1
MCLKOUT


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