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XRT86SH221 Datasheet(PDF) 5 Page - Exar Corporation |
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XRT86SH221 Datasheet(HTML) 5 Page - Exar Corporation |
5 / 357 page XRT86SH221 II REV. 1.0.1 SDH-TO-PDH FRAMER/MAPPER WITH INTEGRATED 21-CHANNEL E1 SH LIU FIGURE 15. TOP LEVEL BLOCK DIAGRAM........................................................................................................................................ 42 4.6 INTERRUPTS AND STATUS ............................................................................................................................ 43 FIGURE 16. INTERRUPT HIERARCHY ............................................................................................................................................... 43 4.7 INTERRUPT PROCESSING AND CONTROL .................................................................................................. 44 4.8 STM-0/1 RECEIVE TRANSPORT PROCESSOR.............................................................................................. 44 FIGURE 17. BYTE_ALIGN BLOCK FUNCTIONAL DIAGRAM .............................................................................................................. 44 TABLE 1: 16-BYTE FRAME FOR TRAIL APID ..................................................................................................................................... 49 FIGURE 18. RECEIVE TRACE BUFFER MEMORY............................................................................................................................... 50 TABLE 2: ADDRESSING SCHEME USED TO ACCESS THE SDH OH BYTES ........................................................................................ 51 FIGURE 19. RECEIVE TRANSPORT OVERHEAD INTERFACE TIMING ................................................................................................... 52 STM-0/1 RECEIVE PATH PROCESSOR................................................................................................. 53 FIGURE 20. POINTER PROCESSING FSM ........................................................................................................................................ 55 TABLE 3: SDH POINTER EVENT TYPES .......................................................................................................................................... 55 FIGURE 21. CONCATENATED POINTER INDICATOR PROCESSING FSM.............................................................................................. 57 TABLE 4: RDI-P SETTINGS AND INTERPRETATION ........................................................................................................................... 58 TABLE 5: STS SIGNAL LABEL MISMATCH DEFECT CONDITIONS ....................................................................................................... 59 TABLE 6: TRUTH TABLE FOR PATH LABEL ERROR CONDITIONS ....................................................................................................... 59 FIGURE 22. PATH OVERHEAD INTERFACE TIMING............................................................................................................................ 62 FIGURE 23. TRANSMIT TRANSPORT OVERHEAD INTERFACE TIMING ................................................................................................. 63 4.9 TELECOM BUS INTERFACE............................................................................................................................ 68 4.9.1 TRANSMIT TELECOM BUS ......................................................................................................................................... 68 FIGURE 24. TRANSMIT TELECOM BUS INTERFACE TIMING................................................................................................................ 68 4.9.2 2KHZ MODE IN STM-1 ................................................................................................................................................. 69 FIGURE 25. C1J1V1 PULSE IN STM-1 2KHZ MODE........................................................................................................................ 69 4.9.3 RECEIVE TELECOM BUS ............................................................................................................................................ 69 FIGURE 26. RECEIVE TELECOM BUS INTERFACE TIMING.................................................................................................................. 69 4.10 VT MAPPER .................................................................................................................................................... 71 FIGURE 27. INTERNAL BUS STRUCTURE ......................................................................................................................................... 71 FIGURE 28. MID BUS INTERFACE.................................................................................................................................................... 73 FIGURE 29. SDH TO VTM DATA TRANSFER WITH ZERO POINTER OFFSET......................................................................................... 73 FIGURE 30. VTM TO SDH DATA TRANSFER .................................................................................................................................... 74 FIGURE 31. E1 INTERFACE TIMING (INTERNAL TO THE CHIP) ........................................................................................................... 75 FIGURE 32. E1 INTERFACE TIMING (E1 SYNCHRONOUS MAPPING, INTERNAL TO THE CHIP)............................................................... 75 TABLE 7: V5 - VT PATH ERROR CHECKING, SIGNAL LABEL AND PATH STATUS ................................................................................ 76 TABLE 8: N2 BYTE STRUCTURE ...................................................................................................................................................... 78 TABLE 9: B7-B8 MULTIFRAME STRUCTURE ....................................................................................................................................... 79 TABLE 10: STRUCTURE OF FRAMES # 73 - 76 OF THE B7-B8 MULTIFRAME ....................................................................................... 79 TABLE 11: K4 (B5-B7) CODING AND INTERPRETATION ...................................................................................................................... 81 TABLE 12: Z7/K4 - VT PATH GROWTH AND VT PATH REMOTE DEFECT INDICATION ........................................................................ 81 FIGURE 33. MKP (MAKE PAYLOAD), ONE OF SEVEN MKG : MAKE VT/TU GROUP ........................................................................... 82 FIGURE 34. MKP (MAKE PAYLOAD), VT/TU GROUP INTERLEAVING................................................................................................. 83 FIGURE 35. MAKE TRIBUTARY (MKT) ............................................................................................................................................. 84 FIGURE 36. EXTRACT PAYLOAD (XTP) ........................................................................................................................................... 85 FIGURE 37. REFERENCE CLOCKS GENERATOR (RCG).................................................................................................................... 86 DATA INTERFACE BETWEEN SDH/FRAMER AND MAPPER .............................................................. 87 FIGURE 38. RECEIVE SDH/FRAMER MAPPER INTERFACE ................................................................................................................ 87 FIGURE 39. TRANSMIT SDH/FRAMER MAPPER INTERFACE .............................................................................................................. 87 FIGURE 40. E1 FRAMER SYNCHRONIZATION FLOW DIAGRAM .......................................................................................................... 88 FIGURE 41. FLOW OF CRC-4 MULTIFRAME ALIGNMENT FOR INTERWORKING .................................................................................... 90 4.11 E1 PHY LOOPBACK DIAGNOSTICS ............................................................................................................. 93 4.11.1 E1 LOOPBACKS......................................................................................................................................................... 93 FIGURE 42. E1 FACILITY LOOPBACK............................................................................................................................................... 93 4.11.2 E1 FACILITY I/O LOOPBACK .................................................................................................................................... 94 FIGURE 43. E1 FACILITY I/O LOOPBACK ......................................................................................................................................... 94 4.11.3 E1 MODULE LOOPBACK ......................................................................................................................................... 95 FIGURE 44. E1 MODULE LOOPBACK................................................................................................................................................ 95 4.11.4 ALARM AND AUTO AIS ............................................................................................................................................. 96 FIGURE 45. E1 AUTO AIS INSERTION ............................................................................................................................................. 96 TABLE 13: E1 TO STM-0 - RESPONSE TIME < 125 US ..................................................................................................................... 96 TABLE 14: STM-0 TO E1 - RESPONSE TIME < 125 USEC ................................................................................................................. 96 5.0 ANALOG FRONT END / LINE INTERFACE UNIT (LIU) SECTION...................................................... 98 FIGURE 46. SIMPLIFIED BLOCK DIAGRAM OF THE LIU SECTION ....................................................................................................... 98 5.1 TRANSMIT LINE INTERFACE UNIT................................................................................................................. 99 5.1.1 JITTER ATTENUATOR................................................................................................................................................. 99 5.1.2 TAOS (TRANSMIT ALL ONES).................................................................................................................................... 99 |
Similar Part No. - XRT86SH221_08 |
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Similar Description - XRT86SH221_08 |
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