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XRT86SH221 Datasheet(PDF) 4 Page - Exar Corporation |
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XRT86SH221 Datasheet(HTML) 4 Page - Exar Corporation |
4 / 357 page XRT86SH221 I SDH-TO-PDH FRAMER/MAPPER WITH INTEGRATED 21-CHANNEL E1 SH LIU REV. 1.0.1 TABLE OF CONTENTS GENERAL DESCRIPTION ................................................................................................ 1 FIGURE 1. SIMPLIFIED BLOCK DIAGRAM ............................................................................................................................................ 1 PACKAGE ORDERING INFORMATION ...................................................................................................... 1 FEATURES ........................................................................................................................ 2 TABLE OF CONTENTS...................................................................................................... I 1.0 PIN DESCRIPTIONS ................................................................................................................................ 4 1.1 MICROPROCESSOR INTERFACE PINS............................................................................................................ 4 1.2 BOUNDARY SCAN AND OTHER TEST PINS.................................................................................................... 6 1.3 GENERAL PURPOSE INPUT AND OUTPUT PINS............................................................................................ 7 1.4 TIMING AND CLOCK SIGNALS.......................................................................................................................... 7 1.5 LOW SPEED LINE INTERFACE SIGNALS ........................................................................................................ 9 1.6 HIGH SPEED SERIAL INTERFACE.................................................................................................................. 12 1.7 HIGH SPEED TELECOM BUS INTERFACE.................................................................................................... 13 1.8 HIGH SPEED SECTION AND PATH OVERHEAD BUS ................................................................................... 15 1.9 HIGH SPEED TU POH OVERHEAD BUS ......................................................................................................... 16 1.10 POWER AND GROUND PINS ......................................................................................................................... 18 2.0 APPLICATIONS AND PHYSICAL INTERFACE GENERAL OVERVIEW............................................. 20 FIGURE 2. APPLICATION DIAGRAM .................................................................................................................................................. 20 2.1 PHYSICAL INTERFACE .................................................................................................................................... 21 FIGURE 3. SIMPLIFIED BLOCK DIAGRAM OF THE PHYSICAL INTERFACE ............................................................................................. 21 2.2 TELECOM BUS INTERFACE ............................................................................................................................ 22 FIGURE 4. SIMPLIFIED BLOCK DIAGRAM OF THE TELECOM BUS INTERFACE ...................................................................................... 22 2.3 STM-0 SERIAL INTERFACE SDH FRAME SYNCHRONIZATION AND TIMING INTERFACE....................... 23 FIGURE 5. SIMPLIFIED BLOCK DIAGRAM OF THE SERIAL PORT INTERFACE ....................................................................................... 23 2.4 SDH FRAME SYNCHRONIZATION AND TIMING INTERFACE ...................................................................... 24 FIGURE 6. SIMPLIFIED BLOCK DIAGRAM OF THE SDH FRAME SYNCHRONIZATION............................................................................. 24 2.5 SDH OVERHEAD ADD-DROP INTERFACES .................................................................................................. 25 FIGURE 7. SIMPLIFIED BLOCK DIAGRAM OF THE SDH OVERHEAD ADD-DROP INTERFACE................................................................. 25 2.6 E1 SHORT HAUL LINE INTERFACE ................................................................................................................ 26 2.7 E1 TIMING INTERFACE .................................................................................................................................... 27 2.8 MICROPROCESSOR INTERFACE ................................................................................................................... 27 3.0 FUNCTIONAL DESCRIPTION ............................................................................................................... 28 FIGURE 8. FUNCTIONAL BLOCK DIAGRAM........................................................................................................................................ 28 3.1 INGRESS DATA PATH FUNCTIONAL BLOCKS ............................................................................................. 29 FIGURE 9. SIMPLIFIED BLOCK DIAGRAM OF THE INGRESS DATA PATH.............................................................................................. 29 3.2 E1 RECEIVE LIU (RXE1LIU) ............................................................................................................................. 29 3.3 TRANSMIT LOW-ORDER (TU) OVERHEAD INSERTION BUS (TXTUPOH) .................................................. 29 3.4 VC-12/TU-12 TRANSMIT LOW-ORDER MAPPER AND OVERHEAD PROCESSOR (TXLOPOHPROC)...... 30 3.5 VC-12 TRANSMIT CROSS-CONNECT (TXVC12XC) ....................................................................................... 30 3.6 TRANSMIT SDH SOH/POH INSERTION BUS (TXOH) .................................................................................... 30 3.7 SDH TRANSMIT MAPPER AND PATH OVERHEAD PROCESSOR (TXPOHPROC) ..................................... 31 3.8 SDH TRANSMIT FRAMER AND SECTION OVERHEAD PROCESSOR (TXSOHPROC) ............................... 32 3.9 TRANSMIT TELECOM BUS (TXTBUS) ............................................................................................................ 33 3.10 EGRESS DATA PATH FUNCTIONAL BLOCKS ............................................................................................ 34 FIGURE 10. SIMPLIFIED BLOCK DIAGRAM OF THE EGRESS DATA PATH ............................................................................................ 34 3.11 RECEIVE TELECOM BUS (RXTBUS)............................................................................................................. 34 3.12 SDH RECEIVE FRAMER AND SECTION OVERHEAD PROCESSOR (RXSOHPROC) ............................... 35 3.13 SDH RECEIVE MAPPER AND PATH OVERHEAD PROCESSOR (RXPOHPROC) ..................................... 36 4.0 VOYAGER-LITE HARDWARE ARCHITECTURE AND ALGORITHMS ............................................... 37 FIGURE 11. VOYAGER-LITE ARCHITECTURE .................................................................................................................................... 37 4.1 MULTIPLEXING STRUCTURE.......................................................................................................................... 38 FIGURE 12. MULTIPLEXING STRUCTURE .......................................................................................................................................... 38 4.2 FUNCTIONAL BLOCKS .................................................................................................................................... 39 4.3 SDH TRANSMIT DATA FLOW .......................................................................................................................... 39 FIGURE 13. SDH TRANSMITTER GENERAL STRUCTURE................................................................................................................... 40 4.4 SDH RECEIVE DATA FLOW............................................................................................................................. 40 FIGURE 14. GENERAL COMPOSITION OF A SDH STM-N RECEIVER ................................................................................................. 41 4.5 VT MAPPER...................................................................................................................................................... 41 |
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